Tiered Memory Cache Using Heat Maps for DRAM-SSD Data Placement
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Solution Overview
Problem
The increasing demand for rapid data access in computer systems is challenging due to the high cost of fast storage solutions like DRAM, while slower storage options like SSDs and hard disk drives are more cost-effective but offer slower access times.
Innovation Solution
A tiered memory device that includes a first memory (DRAM) and a second memory (SSD), with a monitoring circuit that tracks access and miss rates to generate heat and miss maps, enabling improved eviction and prefetching strategies to optimize cache performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is added to increase memory capacity and support faster data access, then data access speed is improved, but system cost increases
Solution Approach 1:
The memory system is segmented into multiple tiers: a first memory device (DRAM) for fast access and a second memory device (SSD/NVMe) for capacity storage. This segmentation allows the system to use a small amount of expensive DRAM for frequently accessed data while storing the bulk of data in cost-effective SSD/NVMe, resolving the contradiction between access speed and cost.
Solution Approach 2:
A cache coherence interconnect protocol is introduced as an intermediary mechanism between the processor and the tiered memory devices. This intermediary enables efficient data transfer and coordination between different memory tiers, allowing the system to achieve fast access speeds without requiring proportionally more expensive DRAM capacity.
2Productivity
If DRAM capacity is increased to meet application data access demands, then data access performance is improved, but cost per unit increases
Solution Approach 1:
The memory architecture is divided into performance-critical tier (DRAM) and capacity tier (SSD/NVMe). By segmenting the memory hierarchy, the system achieves high data access performance for working sets while using cost-effective storage for bulk data, thereby improving productivity without proportionally increasing DRAM cost.
Solution Approach 2:
The system dynamically adjusts memory access parameters by monitoring access patterns and using heat maps to identify hot data regions. This allows the cache manager to optimize which data resides in DRAM versus SSD/NVMe, improving data access performance while minimizing expensive DRAM usage.
3Productivity
If a monitoring circuit tracks access patterns to generate heat maps for optimized cache management, then cache performance is improved, but device complexity increases
Solution Approach 1:
The monitoring circuit automatically tracks access patterns, generates heat maps, and provides eviction/prefetching recommendations without requiring external intervention. This self-service mechanism improves cache performance by continuously adapting to access patterns while keeping the added complexity contained within the memory subsystem itself.
Solution Approach 2:
The system implements a feedback loop where the monitoring circuit tracks access patterns, generates heat maps, and uses this information to adjust cache eviction and prefetching strategies. This feedback mechanism continuously optimizes cache performance while managing complexity through automated adaptive control.
Data Source
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AI summary
A tiered memory device is disclosed. The tiered memory device may include a first memory and a second memory. A monitoring circuit may monitor the first memory to generate a heat map and a miss map based at least in part on a request received from a processor. A policy engine may evict a first data from the first memory to the second memory and may prefetch a second data from the second memory to the first memory based at least in part on the heat map and the miss map.