Tiered Memory ECC Decoding for Low-Latency Error Correction
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Solution Overview
Problem
Current memory devices face challenges in effectively correcting errors across different types of memory systems, particularly in volatile and non-volatile memory, where existing error correction codes (ECC) may fail to correct errors efficiently due to varying latency, power consumption, and error correction capabilities.
Innovation Solution
Implementing a tiered error correction code (ECC) system that progressively applies different ECC operations, starting with low-latency and low-power operations using hard data, followed by iterative decoding with block-wise concatenated codewords, and finally using soft data to correct errors, allowing for adaptive selection based on a-priori information such as memory health and data size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single strong ECC operation is used to ensure high error correction capability, then reliability is improved, but latency and power consumption increase
Solution Approach 1:
The ECC decoding process is segmented into multiple tiers or passes. The first pass uses a simpler, faster decoding algorithm that corrects common error patterns. If errors remain, a second pass with more complex decoding is applied. This segmentation allows the system to achieve high reliability while minimizing average latency by avoiding full complex decoding for all data.
Solution Approach 2:
The system applies partial ECC decoding in the first pass, correcting only the most common error patterns that occur frequently. This partial action handles the majority of cases efficiently. Only when partial decoding fails does the system apply the full, more time-consuming decoding process, thus reducing average latency while maintaining reliability.
2Reliability
If a single strong ECC operation is used to ensure high error correction capability, then reliability is improved, but power consumption increases
Solution Approach 1:
The ECC decoding process is segmented into multiple tiers or passes. The first pass uses a simpler, faster decoding algorithm that corrects common error patterns. If errors remain, a second pass with more complex decoding is applied. This segmentation allows the system to achieve high reliability while minimizing average latency by avoiding full complex decoding for all data.
Solution Approach 2:
The system applies partial ECC decoding in the first pass, correcting only the most common error patterns that occur frequently. This partial action handles the majority of cases efficiently. Only when partial decoding fails does the system apply the full, more time-consuming decoding process, thus reducing average latency while maintaining reliability.
3Reliability
If multiple ECC operations are applied iteratively to correct all errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The ECC decoding process is segmented into multiple tiers or passes. The first pass uses a simpler, faster decoding algorithm that corrects common error patterns. If errors remain, a second pass with more complex decoding is applied. This segmentation allows the system to achieve high reliability while minimizing average latency by avoiding full complex decoding for all data.
Solution Approach 2:
The patent introduces an intermediary syndrome check between ECC decoding passes. After the first ECC decoding pass, the system performs a syndrome check to determine whether errors remain. This intermediary step acts as a mediator that decides whether to proceed to the more complex second decoding pass, thereby managing device complexity by avoiding unnecessary complex operations.
Data Source
AI summary
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.