Tiered 3D Memory Stack With Offset Pillars for Contact Alignment
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Solution Overview
Problem
As the number of tiers in vertical memory arrays increases, forming aligned contacts becomes increasingly difficult, and reducing spacing between vertical memory strings complicates the formation of isolation structures, hindering the advancement of memory density in non-volatile memory devices like NAND Flash memory.
Innovation Solution
The electronic device incorporates a stack with tiers of alternating conductive and insulative structures, featuring horizontally offset pillars that facilitate direct connection to conductive lines without additional contact structures, and a weave pattern of slots for improved electrical isolation and reduced resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of tiers in vertical memory arrays is increased to increase memory density, then memory density is improved, but the difficulty of forming aligned contacts increases
Solution Approach 1:
The patent transitions from conventional planar contact structures to three-dimensional vertically-offset contact structures. Contact structures are positioned at different vertical levels (tiers) rather than requiring precise horizontal alignment, thereby resolving the alignment difficulty while maintaining high memory density through vertical stacking of memory tiers.
Solution Approach 2:
The patent divides the contact structure into multiple segmented contact regions, each aligned with specific tiers of the vertical memory array. This segmentation allows independent formation and alignment of contacts for different memory tiers, reducing the overall alignment complexity compared to forming a single continuous contact structure.
2Quantity of substance
If the spacing between adjacent vertical memory strings is reduced to increase memory density, then memory density is improved, but the difficulty of forming isolation structures increases
Solution Approach 1:
The patent implements isolation structures that are nested within the vertical memory string architecture itself. The isolation regions are formed as part of the vertical stacking process, with insulative structures integrated between and around the memory strings, allowing tight spacing while maintaining manufacturability through combined formation steps.
3Reliability
If additional contact structures are used to connect conductive structures to access lines, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The patent merges the contact structure with the vertical memory string architecture by integrating conductive regions directly into the stacked memory tiers. This consolidation eliminates the need for separate additional contact structures, reducing device complexity while maintaining reliable electrical connectivity through the integrated conductive pathways.
Data Source
AI summary
An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.