Tiered Memory Page Migration Using Split Control and Data Planes
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Solution Overview
Problem
In tiered memory systems, coupling the control plane for determining access frequency and the data plane for performing page migration in a single thread leads to performance degradation due to cache invalidation and limited cache memory capacity, especially when accessing slower memories.
Innovation Solution
A method for page migration in a tiered memory system where different cores handle the control and data planes independently, using hardware-based event sampling to determine hot or cold pages and generate migration requests based on access counts, and performing page migrations through direct memory access to optimize memory allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the control plane and data plane are coupled in a single thread, then the system structure is simpler, but performance degrades due to cache invalidation and limited cache memory capacity
Solution Approach 1:
The patent divides the control plane and data plane into separate threads. The control plane thread handles page fault detection and migration decisions, while the data plane thread executes actual data migration operations. This segmentation eliminates cache invalidation issues and allows each plane to operate independently with optimized cache management, resolving the contradiction between structural simplicity and performance.
2Productivity
If page migration is performed frequently to optimize memory allocation, then memory access performance improves, but overhead increases due to periodic page faults and TLB flushes
Solution Approach 1:
The patent implements preliminary actions by proactively identifying pages that need migration before they cause performance degradation. The control plane monitors memory access patterns and preemptively migrates pages between memory tiers, avoiding the need for reactive page fault handling and reducing TLB flush overhead associated with periodic migrations.
3Measurement precision
If access frequency is determined using scanning or page fault induction, then data classification improves, but application program performance degrades
Solution Approach 1:
The patent enables the memory system to self-determine access frequency by monitoring actual memory access patterns without requiring external scanning operations or inducing page faults. The control plane thread passively collects access information and automatically classifies pages based on observed behavior, eliminating the performance penalty associated with active scanning and induction methods while maintaining accurate access frequency detection.
Data Source
AI summary
A page migration method performed by a processor including cores includes: reading, from a ring buffer, by a first core, samples of access events for memories connected with the cores; increasing, by the first core, an access count of a first page of a first memory among the memories based on the read samples of the access events; determining, by the first core, whether the first page is a hot page or a cold page based on the access count; generating, by the first core, a migration request to migrate the first page to a second memory among the memories depending on whether the first page is determined to be a hot page or a cold page; and performing, by a second core, migration of the first page from the first memory to the second memory based on the migration request.