Tiered Memory Controller Allocating Data by Quality Metrics
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Solution Overview
Problem
In tiered memory systems, existing technologies fail to optimally utilize memory locations based on their reliability and access speed, leading to inefficient data storage and potential data loss due to bit error rates and degradation over time.
Innovation Solution
A memory controller is configured to store redundant data in less reliable secondary memory locations and non-redundant data in more reliable locations, dynamically adjusting usage based on quality metrics such as bit error rate and access speed, thereby reserving superior quality memory locations for critical data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory locations are used uniformly for all data storage, then the memory system is simple to manage, but reliable memory locations are wasted on redundant data while unreliable locations store critical non-redundant data
Solution Approach 1:
The patent applies local quality by differentiating memory location quality and assigning different data types to different quality locations. Specifically, high-quality memory locations (with lower bit error rates) are reserved for non-redundant data, while low-quality locations are used for redundant data. This resolves the contradiction by making the memory system heterogeneous in its usage, matching data criticality to location reliability, thereby improving overall reliability without requiring complete redesign of the memory architecture.
Solution Approach 2:
The patent segments the secondary memory into different quality-based regions for storing different types of data. By dividing the memory space into high-quality and low-quality location segments, the system can strategically place non-redundant data in high-quality segments and redundant data in low-quality segments. This segmentation approach improves reliability while maintaining manageable complexity through structured organization.
2Reliability
If high-quality memory locations are used for all data, then data reliability is maximized, but access speed and cost efficiency decrease
Solution Approach 1:
The patent applies local quality by matching memory location quality to data criticality. High-quality locations with better bit error rates are allocated specifically for non-redundant data that requires high reliability, while low-quality locations are used for redundant data where errors can be corrected. This selective allocation ensures that access speed is optimized by not forcing all data through high-quality (slower) paths, while still protecting critical data with appropriate quality locations.
3Reliability
If redundant data is stored in high-quality memory locations, then data integrity is improved, but memory resource utilization and lifespan are reduced
Solution Approach 1:
The patent applies local quality by assigning redundant data to low-quality memory locations and non-redundant data to high-quality locations. This strategy improves overall data integrity because non-redundant data (which cannot be recovered if lost) is protected by high-quality locations with lower bit error rates. Simultaneously, memory lifespan is extended because the more durable high-quality locations are not subjected to the wear and error-prone operations of storing redundant data, which can be regenerated or corrected.
Solution Approach 2:
The patent treats low-quality memory locations as disposable or sacrificial resources for storing redundant data. These locations have higher bit error rates and shorter effective lifespans, but since they store redundant data that can be corrected or regenerated, the system can tolerate their degradation. This allows the more expensive, durable high-quality locations to be preserved for critical non-redundant data, thereby extending overall system lifespan while maintaining data integrity.
Data Source
AI summary
A tiered memory system includes a memory controller for a primary memory and a secondary memory, where the secondary memory is used as a cache for the primary memory. The memory controller is configured to cause redundant data that is stored in the primary memory of the memory system to be stored in first memory locations of the secondary memory. The controller causes data that is not stored in the primary memory to be stored in second memory locations of the secondary memory. The second memory locations have at least one of lower bit error rate and higher access speed than the first memory locations.