Tiered Memory Ranks for Power-Constrained Capacity

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Solution Overview

Problem

Power-constrained data processing systems face limitations in memory capacity due to restricted power budgets, leading to performance degradation from frequent page-outs and page-ins, as existing methods either conserve power by degrading performance or accept performance degradation to conserve power.

Innovation Solution

Implementing a tiered memory organization with a hot tier for frequently accessed pages in active mode and a cold tier for infrequently accessed pages in low-power mode, allowing for increased memory capacity while maintaining power consumption within the budget by throttling requests and dynamically reconfiguring ranks based on workload demands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory size is increased to improve application performance, then memory capacity increases, but power consumption increases

Engineering Contradiction:
Improvememory capacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The memory system is divided into multiple ranks that can be independently controlled and powered. This segmentation allows the system to activate only the necessary portion of memory capacity based on current workload requirements, rather than powering the entire memory array, thus providing increased capacity when needed while consuming less power during normal operation.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If power budget is constrained to reduce power consumption, then power usage decreases, but memory capacity is limited

Engineering Contradiction:
Improvepower consumptionVSAvoidmemory capacity
Core Design Contradiction:
Use of energy by moving objectVSQuantity of substance

Solution Approach 1:

The memory system implements dynamic power management where ranks can be dynamically activated or deactivated based on real-time workload demands. The system monitors memory access patterns and adjusts the number of active ranks accordingly, allowing the memory capacity to dynamically scale with the workload while maintaining power consumption within the budget constraints.

Inventive Principle:
Principle #15Dynamics

3Use of energy by moving object

If memory capacity is limited to conserve power, then power consumption decreases, but page-out and page-in operations increase

Engineering Contradiction:
Improvepower consumptionVSAvoidapplication performance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The system proactively manages memory ranks by keeping potentially needed memory pages in active ranks before they are actually accessed. By monitoring access patterns and pre-loading data into the limited active memory capacity, the system reduces the frequency of page-outs to secondary storage and subsequent page-ins, thereby improving application performance while maintaining power-constrained operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8719527B2Increasing memory capacity in power-constrained systems
Publication Date: 2014.05.06 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8719527B2 patent drawing
  • US8719527B2 patent drawing
  • US8719527B2 patent drawing

AI summary

A method for increasing a capacity of a memory is provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.