Tiered Power Savings in Instruction Loop Buffers

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Solution Overview

Problem

Existing processor technologies consume unnecessary power during instruction loops, as they often require a large number of loop iterations to initiate power-saving modes, which is inefficient, especially in battery-powered devices.

Innovation Solution

Implementing a loop control circuit that detects instruction loops and switches between multiple power-saving modes, reducing power consumption by clock-gating or powering off certain structures, such as the instruction cache and branch predictor, after initial loop observations, even for small loops.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor waits for a large number of loop iterations (e.g., 20+) before entering power-saving mode, then it can ensure the loop has reached steady state, but power consumption remains high during the initial iterations

Engineering Contradiction:

Improvesteady state detection accuracyVSAvoidpower consumption during loop execution

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The power-saving approach is segmented into multiple tiers: a first tier that activates after a small number of loop iterations (e.g., 2-3) providing initial power savings, and a second tier that activates after more iterations (e.g., 20+) providing deeper power savings. This segmentation allows the system to begin saving power immediately rather than waiting for steady state, while still achieving maximum savings when confidence is high.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts the level of power saving based on the observed number of loop iterations. Rather than using a fixed threshold, the power-saving mode evolves from a first level (less aggressive) to a second level (more aggressive) as more loop iterations are observed, allowing the system to balance between early power savings and steady-state accuracy.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If the processor enters power-saving mode after only a few loop iterations, then power savings begin immediately, but the loop may not have reached steady state reducing prediction accuracy

Engineering Contradiction:

Improvepower consumption during loop executionVSAvoidbranch prediction accuracy

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of power-saving aggressiveness based on loop iteration count. The first power-saving mode uses a conservative parameter set that maintains higher prediction accuracy, while the second power-saving mode uses a more aggressive parameter set that achieves deeper power savings when sufficient iterations have confirmed the loop pattern.

Inventive Principle:

Principle #35Parameter changes

3Use of energy by moving object

If dedicated loop buffer structures are implemented, then power savings during loop execution are maximized, but device complexity and area increase

Engineering Contradiction:

Improvepower consumption during loop executionVSAvoidprocessor structure complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The instruction buffer, which normally serves general instruction storage purposes, is made multi-functional by enabling it to serve as a loop buffer when a loop is detected. This eliminates the need for a separate dedicated loop buffer structure, achieving the power-saving benefits of a specialized structure without the associated area and complexity costs.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the general instruction buffer and the specialized loop buffer functions into a single structure. By combining these functions, the system achieves the power-saving benefits of a dedicated loop buffer while avoiding the area overhead and complexity of maintaining separate structures.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9524011B2Instruction loop buffer with tiered power savings

Publication Date: 2016.12.20 APPLE INC

AI summary

Techniques are disclosed relating to power reduction during execution of instruction loops. Multiple different power saving modes may be used by a processor, such as a first power saving mode after only a few loop iterations (e.g., 2-3) and a second, deeper power saving mode after a greater number of loop iterations. The first power saving mode may include keeping a branch predictor and/or other structures active, but the second power saving mode may include reducing power to the branch predictor and/or other structures. An observation mode and an instruction capture mode may also be used by a processor prior to entering a power saving mode for loop execution. Power saving modes may also be achieved during execution of complex loops having multiple backward branches (e.g., nested loops).