Tiered Semiconductor Alignment Testing via Via Diameter and Offset Measurement
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Solution Overview
Problem
The challenge in tiered semiconductor structures, such as stacked CMOS structures, is misalignment, incomplete tunneling, or over tunneling during the stacking process due to the small size of tier-to-tier vias, leading to yield loss and other penalties.
Innovation Solution
A method and system for evaluating tiered semiconductor structures by measuring via diameter and offset distance between layers, using a conductive arc to assess alignment rotation, and forming test structures on the wafer edge or within the device to detect misalignment, allowing for early detection and repair during the stacking process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tier-to-tier vias are made smaller to achieve higher integration density, then the stacking capacity is improved, but misalignment and tunneling defects increase leading to yield loss
Solution Approach 1:
The patent performs alignment testing and measures via diameter and offset distance before completing the stacking process. Test structures are formed on wafer edges or within devices to detect misalignment early, allowing for corrective actions before full assembly is completed, thereby preventing yield loss from misalignment while maintaining small via sizes for high integration density
Solution Approach 2:
The patent implements a feedback mechanism by measuring via diameter and offset distance through alignment testing, then using this information to evaluate and adjust the stacking process. This feedback loop enables real-time monitoring and correction of alignment issues, maintaining manufacturing precision while achieving high stacking capacity through small vias
2Reliability
If alignment testing is performed during stacking process, then misalignment can be detected early for repair, but the testing and measurement process adds complexity to the manufacturing system
Solution Approach 1:
The patent extracts alignment testing functions to be performed on wafer edges or within dedicated test structures separate from the main device fabrication. This allows alignment measurement and evaluation to be conducted using simplified test structures rather than requiring complex testing of complete devices, reducing testing system complexity while maintaining stacking yield through early defect detection
Data Source
AI summary
Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.