Tiered Virtual Ground Regulation for SoC Leakage and Data Retention

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Solution Overview

Problem

Static leakage power consumption is a significant challenge in very large scale system-on-a-chip (SoC) integrated circuits, particularly in handheld devices, as it increases with finer geometry manufacturing processes, making it difficult to meet chip leakage targets using traditional power reduction techniques.

Innovation Solution

A data processor with multiple low power modes is implemented, utilizing virtual ground terminals and tiered voltage regulators to selectively adjust power supply voltages, ensuring data retention while minimizing leakage current by enabling or disabling voltage regulators based on operating modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If voltage regulators are used to reduce leakage current by elevating virtual ground potential, then static leakage power consumption is reduced, but data retention voltage requirements may be violated causing data corruption

Engineering Contradiction:
Improvestatic leakage power consumptionVSAvoiddata retention
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The voltage regulator system is segmented into a global voltage regulator for overall leakage reduction and multiple local voltage regulators for specific circuit blocks. This segmentation allows selective application of leakage reduction techniques to different parts of the system, enabling leakage current reduction while maintaining data retention voltage requirements for critical blocks like cache memories through independent control of each segment's virtual ground elevation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts the virtual ground potential elevation based on operational requirements. The global and local voltage regulators are controlled to provide different levels of virtual ground elevation depending on whether data retention is required, allowing the system to transition between leakage reduction modes and data retention modes as needed.

Inventive Principle:
Principle #15Dynamics

2Productivity

If finer geometry manufacturing processes are used to increase transistor density, then processing capacity is improved, but transistor leakage currents increase

Engineering Contradiction:
Improveprocessing capacityVSAvoidtransistor leakage current
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The invention changes the electrical parameters of the system by elevating the virtual ground potential above actual ground potential. This parameter change affects the voltage differential across transistors, thereby reducing leakage currents. The global voltage regulator implements this parameter change system-wide, while local voltage regulators can apply it selectively to specific circuit blocks experiencing high leakage.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8489906B2Data processor having multiple low power modes
Publication Date: 2013.07.16 NXP USA INC
  • US8489906B2 patent drawing
  • US8489906B2 patent drawing
  • US8489906B2 patent drawing

AI summary

A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.