Tightly Coupled Differential Vias Crosstalk Reduction
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Solution Overview
Problem
Conventional differential via designs in high-speed SerDes systems face challenges with signal discontinuity and crosstalk issues due to the spacing and impedance mismatch between vias, which affect signal integrity and data rate performance.
Innovation Solution
The proposed solution involves tightly coupling differential vias by placing them relatively close to each other with specific spacing and impedance configurations, such as a differential via impedance of 85 Ohms and single-ended via impedance of 42 Ohms, to minimize crosstalk and maintain signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If differential vias are placed close to each other, then crosstalk between differential pairs is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the two vias of a differential pair into a tightly coupled configuration where the vias are positioned immediately adjacent to each other (e.g., 0.1mm spacing). This merging approach causes the electromagnetic fields of the two vias to interact and cancel each other's interference, thereby reducing crosstalk with neighboring differential pairs while maintaining signal integrity.
Solution Approach 2:
The patent changes the spacing parameter between differential vias from conventional larger distances to a tightly coupled small distance (e.g., 0.1mm or less). This parameter change fundamentally alters the electromagnetic field distribution and coupling characteristics, transforming the via structure from isolated to tightly coupled, which reduces crosstalk but increases sensitivity to manufacturing variations.
2Reliability
If via spacing is reduced to minimize crosstalk, then signal integrity improves, but impedance control becomes more difficult
Solution Approach 1:
The patent changes the impedance parameter of the differential via structure by adjusting via diameter, depth, and spacing. For example, reducing via diameter or increasing via depth can compensate for the reduced spacing, allowing the differential impedance to be maintained at the target value (e.g., 100 Ohms) even in a tightly coupled configuration, thus preserving signal integrity while minimizing crosstalk.
Solution Approach 2:
The patent introduces reference planes (ground or power planes) as intermediary structures between and around the differential vias. These reference planes provide a controlled impedance environment by serving as return paths for signals and shielding elements, helping to maintain consistent differential impedance despite the reduced via spacing, thereby facilitating both signal integrity and impedance control.
3Area of stationary object
If tightly coupled differential vias are used, then PCB real estate is reduced, but trace routing complexity increases
Solution Approach 1:
The patent merges the routing paths of differential pairs by placing vias in a tightly coupled manner and maintaining consistent spacing between traces. This merging approach allows traces to be routed closer together without increasing crosstalk, thereby reducing the overall PCB area required while the standardized routing methodology keeps complexity manageable.
Solution Approach 2:
The patent applies local quality by maintaining different spacing requirements in different regions: tightly coupled vias (0.1mm spacing) within differential pairs to reduce crosstalk, while allowing greater spacing between adjacent differential pairs. This localized differentiation optimizes PCB real estate usage without uniformly increasing routing complexity across the entire board.
Data Source
AI summary
Systems and methods for tightly coupled differential vias are described. the storage system device includes a storage drive and a printed circuit board (PCB) of the storage drive. In some embodiments a first via is connected to a first trace routed on a first layer of the PCB, and a second via is connected to a second trace routed on the first layer of the PCB. In some cases, a distance between the first via and the second via is about 1.5 times or less a spacing between the first trace and the second trace.