Tile-Based Graphics Processing System Transaction Elimination

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Solution Overview

Problem

Graphics processing systems face significant power consumption and memory bandwidth issues due to frequent writing of data to frame buffers, especially in high-resolution displays, with existing techniques like on-chip frame buffers, caching, and compression having drawbacks such as resource requirements, complexity, and image quality loss.

Innovation Solution

A method where the graphics processing system generates data in blocks (tiles) and compares each block with existing data in the output buffer before writing, determining whether to write based on the comparison, thereby reducing unnecessary transactions and conserving power and bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If frame buffer operations are performed frequently to maintain high-resolution display output, then image quality is maintained, but power consumption and memory bandwidth usage increase significantly

Engineering Contradiction:
Improveimage qualityVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent performs a comparison between the current frame buffer data and previous frame data before actually writing to the frame buffer. This preliminary action (comparison) identifies which blocks have changed, allowing the system to skip unnecessary write operations and reduce power consumption while maintaining image quality by only updating changed regions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent divides the frame buffer into multiple blocks and processes them independently. By segmenting the frame buffer into smaller manageable blocks, the system can compare and update only the necessary blocks rather than the entire frame buffer, reducing overall power consumption and memory bandwidth usage.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If frame buffer operations are performed frequently to maintain high-resolution display output, then image quality is maintained, but memory bandwidth usage increases significantly

Engineering Contradiction:
Improveimage qualityVSAvoidmemory bandwidth usage
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The comparison operation serves as a preliminary action that identifies which frame buffer blocks require updates. By performing this comparison before writing, the system avoids transferring unnecessary data over the memory bus, thereby reducing memory bandwidth consumption while ensuring that only necessary updates are performed to maintain image quality.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

By dividing the frame buffer into blocks and processing them individually, the patent enables selective updating of only those blocks that have changed. This segmentation approach reduces the total volume of data transferred to and from memory, decreasing memory bandwidth usage while maintaining complete image quality through precise block-level updates.

Inventive Principle:
Principle #1Segmentation

3Use of energy by moving object

If on-chip frame buffer is used to reduce power consumption, then power usage decreases, but on-chip resource requirements increase significantly

Engineering Contradiction:
Improvepower consumptionVSAvoidon-chip resources
Core Design Contradiction:
Use of energy by moving objectVSVolume of stationary object

Solution Approach 1:

The patent segments the frame buffer into blocks and implements comparison logic that operates on individual blocks. This segmentation allows the system to use minimal on-chip resources for storing and comparing block data, avoiding the need for a large on-chip frame buffer while still achieving power consumption reduction through selective updating of only changed blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts only the essential comparison function and implements it with minimal on-chip resources. By taking out only the necessary comparison logic and block-level processing capabilities, the system achieves power consumption reduction without requiring significant on-chip resource allocation for a full on-chip frame buffer.

Inventive Principle:
Principle #2Taking out (Extraction)

4Use of energy by moving object

If frame buffer compression is used to reduce power consumption and bandwidth usage, then power and bandwidth consumption decrease, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcompression logic complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent performs a simple comparison operation as a preliminary action before frame buffer writing. This comparison is much less complex than compression logic, yet achieves similar power and bandwidth savings by identifying and skipping unchanged blocks, thereby reducing device complexity while maintaining power efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of using complex compression logic to reduce data size, the patent uses a simpler approach of copying only the changed blocks to the frame buffer. This block-level copying mechanism achieves power and bandwidth reduction without requiring the complexity of compression algorithms, hardware or software.

Inventive Principle:
Principle #26Copying

5Use of energy by moving object

If dynamic colour depth control is used to reduce power consumption, then power usage decreases, but image quality is reduced due to lossy compression

Engineering Contradiction:
Improvepower consumptionVSAvoidimage quality
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent performs a preliminary comparison between current and previous frame buffer blocks to identify unchanged regions. This comparison-based approach reduces power consumption by skipping writes to unchanged blocks without altering colour depth or applying lossy compression, thereby maintaining full image quality while achieving power savings through selective updating.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9881401B2Graphics processing system
Publication Date: 2018.01.30 ARM LTD
  • US9881401B2 patent drawing
  • US9881401B2 patent drawing
  • US9881401B2 patent drawing

AI summary

A transaction elimination hardware unit controls the writing to a frame buffer in a memory of tiles generated by a tile-based graphics processor. The transaction elimination hardware unit has a signature generator that generates a signature representative of the content of the tile for each tile. A signature comparator then compares the signature of a new tile received from the graphics processor with the signatures of one or more tiles already stored in the frame buffer to see if the signatures match. If the signatures do not match, then the signature comparator controls a write controller to write the new tile to the frame buffer. On the other hand, if the signatures match, then no data is written to the frame buffer and the existing tile is allowed to remain in the frame buffer. In this way, a tile is only written to the frame buffer if it is found by the signature comparison to differ from the tile or tiles that are already stored in the frame buffer that it is compared with.