Tile-Based Processor Architecture Using Data Communication Links
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Solution Overview
Problem
Current embedded systems face challenges in supporting complex functionalities and high computational throughput while adhering to real-time constraints, due to limited power efficiency and programmability, especially with the increasing complexity of algorithms and standards, and the limitations of transistor scaling in deep sub-micron technology nodes.
Innovation Solution
A processor architecture utilizing data communication links (DCLs) for explicit point-to-point communication and data management between processing elements, allowing for efficient parallel execution and synchronization without the need for complex register files or central data pools, thereby enhancing power efficiency and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor scaling is used to increase computation capabilities, then the number of transistors increases, but power consumption increases without significant reduction
Solution Approach 1:
The system segments computation into parallel processing elements that can operate independently, allowing selective activation of only the processing elements needed for a given task, thereby improving computation capabilities while reducing overall power consumption compared to scaling all transistors
2Adaptability or versatility
If complex algorithms and standards are supported, then functionality is enhanced, but power efficiency deteriorates
Solution Approach 1:
The system dynamically configures and activates processing elements based on the specific algorithm or standard being executed, allowing full functionality support while optimizing power efficiency by only activating the necessary processing resources for each task
Solution Approach 2:
The processing elements are designed with universal functionality to support multiple algorithms and standards, eliminating the need for dedicated hardware for each standard and thereby improving power efficiency through shared resource utilization
3Ease of operation
If traditional register files and central data pools are used, then data communication is simplified, but power consumption and complexity increase
Solution Approach 1:
The system extracts and eliminates the traditional central register file and data pool, replacing them with direct point-to-point communication paths between processing elements, thereby reducing power consumption and complexity while maintaining data communication functionality
Solution Approach 2:
The system introduces DCLs as intermediary communication structures that enable explicit data management and communication between processing elements without requiring a central data pool, achieving both power efficiency and ease of operation
Data Source
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AI summary
The present invention relates to a processor which comprises processing elements that execute instructions in parallel and are connected together with point-to-point communication links called data communication links (DCL). The instructions use DCLs to communicate data between them. In order to realize those communications, they specify the DCLs from which they take their operands, and the DCLs to which they write their results. The DCLs allow the instructions to synchronize their executions and to explicitly manage the data they manipulate. Communications are explicit and are used to realize the storage of temporary variables, which is decoupled from the storage of long-living variables.