Tile-Based Sequence Alignment Memory Optimization
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Solution Overview
Problem
Current sequence alignment algorithms face performance, scalability, accuracy, efficiency, and applicability limitations due to quadratic time and memory requirements, sensitivity to error rates, and overspecialization in hardware designs, which hinder their ability to efficiently handle long and noisy genomic sequences.
Innovation Solution
A method that computes differential encodings of edit distances in tiles of dimension T × T, storing only the elements at the edges of each tile, significantly reducing memory requirements and enabling faster alignment computations, and a computation module designed for this purpose that can be integrated into conventional CPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If classical dynamic programming algorithms are used for sequence alignment, then alignment accuracy is maintained, but execution time and memory consumption increase quadratically with sequence length
Solution Approach 1:
The patent divides the sequence alignment problem into smaller sub-problems by processing sequences in segments or using banded dynamic programming, where only a subset of the DP matrix is computed. This segmentation allows the algorithm to maintain accuracy for the regions of interest while avoiding the quadratic complexity of computing the entire matrix, thus reducing execution time significantly.
Solution Approach 2:
The patent applies local quality by focusing computational resources on specific regions of the DP matrix that are most likely to contain the optimal alignment, such as bands around the diagonal or regions with high probability of matches. This selective computation maintains accuracy where needed while reducing overall execution time by skipping computations in less relevant regions.
2Measurement precision
If classical dynamic programming algorithms are used for sequence alignment, then alignment accuracy is maintained, but memory consumption increases quadratically with sequence length
Solution Approach 1:
The patent segments the DP matrix computation into smaller manageable blocks that can be processed and discarded sequentially. By dividing the large matrix into smaller segments, the algorithm maintains only the necessary portions in memory at any given time, reducing peak memory consumption from quadratic to linear or sub-quadratic while preserving alignment accuracy through systematic processing of all segments.
Solution Approach 2:
The patent applies local quality by storing and computing only the relevant portions of the DP matrix, such as bands around the diagonal where optimal alignments are most likely to occur. This selective storage reduces memory consumption by eliminating the need to maintain the entire quadratic matrix in memory, while still achieving accurate alignments in the regions of interest.
3Productivity
If bit-parallel techniques are used to accelerate sequence alignment, then execution speed improves, but the algorithms become sensitive to error rates and require preprocessing
Solution Approach 1:
The patent applies preliminary action by performing preprocessing steps such as error correction, filtering, or quality score assignment before applying bit-parallel alignment algorithms. This preliminary processing reduces the impact of errors and noise in the input sequences, making the subsequent bit-parallel computation more reliable and less sensitive to error rates while maintaining high execution speed.
Solution Approach 2:
The patent incorporates feedback mechanisms where alignment results are evaluated and used to adjust subsequent computation parameters or to validate results against expected error thresholds. This feedback loop allows the algorithm to detect and correct errors introduced by bit-parallel approximations, improving reliability while maintaining the speed advantages of bit-parallel techniques.
4Productivity
If hardware accelerators are designed for sequence alignment, then computation efficiency improves, but device complexity and cost increase
Solution Approach 1:
The patent designs hardware accelerators with universal architectures that can perform multiple sequence alignment operations and support different alignment algorithms through reconfigurable logic or parameterized designs. This multi-functionality allows a single hardware device to handle various sequencing technologies and analysis tasks, improving computation efficiency while reducing overall device complexity compared to dedicated specialized hardware for each specific task.
Data Source
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AI summary
The present invention discloses a method and computation module (11) for implementing said method for accelerating an alignment algorithm to align sequences (1) of information in which, from the initial algorithm, two input vectors (9, 10) based on differential encoding allocating vertical and horizontal differences of the edit distance of the sequences (1) are computed. These vectors (9, 10) are used to compute a first tile (7) of dimension T x T, both for the vertical and horizontal difference matrices (5, 6), and only the last column or row within the tile (7) is stored in memory. This computation is repeated for adjacent tiles (7) using as input the adjacent column or row stored. Finally, from a starting position, the traceback (4) of a whole tile (7) of dimension T x T is computed and the ending position of such traceback (4) is stored in memory. The aligned sequences (1) corresponding to the traceback (4) of the tile (7) are stored and the traceback (4) of a new, adjacent tile (7) is computed in the same way until the sequences (1) have been aligned.