Tile Buffer Deferred Shading On-Chip Processing
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Solution Overview
Problem
Current graphics processing systems face significant bandwidth and power consumption issues during deferred shading operations, particularly in tile-based graphics processing pipelines, due to the need for frequent external memory reads and writes.
Innovation Solution
A method and system that includes a programmable processing stage within the graphics processing pipeline, allowing for the storage and processing of multiple render targets in a tile buffer, enabling deferred shading operations to be performed on-chip with zero external bandwidth cost by reading and writing data directly within the tile buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deferred shading operations are performed using conventional graphics processing pipelines, then the rendering quality and visual effects are improved, but bandwidth consumption and power usage increase significantly due to frequent external memory reads and writes
Solution Approach 1:
The patent divides the frame buffer into multiple tile buffers, each storing a portion of the render targets. This segmentation allows the programmable processing stage to access only the relevant tile buffer data locally, eliminating the need for frequent external memory transactions and reducing power consumption while maintaining rendering quality
Solution Approach 2:
The patent introduces a new dimension of processing by enabling the programmable processing stage to directly read and write tile buffer data without external memory intervention. This dimensional change in the data access path eliminates bandwidth bottlenecks and reduces power usage associated with external memory transactions
2Reliability
If deferred shading operations are performed using conventional graphics processing pipelines, then the rendering quality and visual effects are improved, but bandwidth consumption and power usage increase significantly due to frequent external memory reads and writes
Solution Approach 1:
The patent divides the frame buffer into multiple tile buffers, each storing a portion of the render targets. This segmentation allows the programmable processing stage to access only the relevant tile buffer data locally, eliminating the need for frequent external memory transactions and reducing power consumption while maintaining rendering quality
Solution Approach 2:
The patent introduces a new dimension of processing by enabling the programmable processing stage to directly read and write tile buffer data without external memory intervention. This dimensional change in the data access path eliminates bandwidth bottlenecks and reduces power usage associated with external memory transactions
3Loss of information
If multiple render targets are stored in external memory for deferred shading operations, then the completeness and accuracy of rendering data are improved, but the time and power required for data access increase
Solution Approach 1:
The patent divides the frame buffer into multiple tile buffers, each storing a portion of the render targets. This segmentation allows the programmable processing stage to access only the relevant tile buffer data locally, eliminating the need for frequent external memory transactions and reducing power consumption while maintaining rendering quality
Solution Approach 2:
The patent performs preliminary actions by storing render target data in tile buffers before the deferred shading operations are executed. This pre-positioning of data in local memory eliminates the need for time-consuming external memory transactions during the actual processing, reducing data access time while maintaining data completeness
4Loss of information
If multiple render targets are stored in external memory for deferred shading operations, then the completeness and accuracy of rendering data are improved, but the time and power required for data access increase
Solution Approach 1:
The patent divides the frame buffer into multiple tile buffers, each storing a portion of the render targets. This segmentation allows the programmable processing stage to access only the relevant tile buffer data locally, eliminating the need for frequent external memory transactions and reducing power consumption while maintaining rendering quality
Solution Approach 2:
The patent performs preliminary actions by storing render target data in tile buffers before the deferred shading operations are executed. This pre-positioning of data in local memory eliminates the need for time-consuming external memory transactions during the actual processing, reducing data access time while maintaining data completeness
Data Source
AI summary
A tile-based graphics processing pipeline 1 comprising a rasteriser 3, a renderer 6, a tile buffer 10, a write out stage 13 and a programmable processing stage 14. The tile buffer 10 stores multiple render targets for a deferred shading operation and the programmable processing stage 14 is operable to, under the control of graphics program instructions, read data from two or more of a set of multiple render targets for a deferred shading operation stored in the tile buffer 10, perform a deferred shading processing operation using the read data, and to write the result of the processing operation to an output render target in the tile buffer 10, or to external memory.