Tile Coalescer for API Order Preservation in Programmable Blending

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Solution Overview

Problem

Conventional graphics processing pipelines lack the ability to perform programmable blending operations while maintaining application programming interface (API) order, as they rely on fixed-function hardware units that are limited in functionality and cannot be programmed like pixel shaders.

Innovation Solution

A graphics subsystem is configured to generate tiles of coverage samples, using a bin to collect and a tile engine to compare and insert coverage samples, allowing programmable blending operations to be performed while maintaining API order by ensuring atomicity and order preservation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fixed-function ROP hardware is used for blending operations, then API order is maintained, but blending functionality is limited

Engineering Contradiction:
Improveblending functionalityVSAvoidhardware functionality
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent enables the ROP to perform both traditional fixed-function blending operations and programmable pixel shader operations through a unified hardware structure. The ROP can be dynamically configured to execute different types of operations including basic blending, complex programmable blending, and pixel shading, making it a universal processing unit that adapts to various rendering needs without requiring separate dedicated hardware for each function type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces dynamic configurability to the ROP hardware, allowing it to switch between different operational modes and processing functions based on the rendering pipeline's current needs. The hardware can be programmed and reconfigured on-the-fly to perform different blending operations, transforming it from a static fixed-function unit to a dynamic programmable unit that maintains API order while providing versatile blending capabilities.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If pixel shader performs pixel blending operations, then programmable operations are possible, but API order is not maintained

Engineering Contradiction:
Improveprogrammable operationsVSAvoidAPI order
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces an intermediary ordering mechanism between the pixel shader and the final output stage. This intermediary structure tracks and enforces API order for pixel operations, ensuring that programmable blending operations performed by the pixel shader maintain the correct rendering order. The intermediary acts as a mediator that allows programmable flexibility while preserving the reliability of API order through systematic tracking and enforcement of operation sequences.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If conventional ROP is used, then API order is maintained, but programmable operations cannot be performed

Engineering Contradiction:
Improveprogrammable operationsVSAvoidhardware programmability
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent transforms the conventional ROP into a universal processing unit that can perform both traditional fixed-function blending and programmable pixel shader operations. By integrating programmable functionality directly into the ROP hardware while maintaining its existing blending capabilities, the system achieves multi-functionality without requiring entirely separate processing units, thus improving adaptability while controlling the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10019776B2Techniques for maintaining atomicity and ordering for pixel shader operations
Publication Date: 2018.07.10 NVIDIA CORP
  • US10019776B2 patent drawing
  • US10019776B2 patent drawing
  • US10019776B2 patent drawing

AI summary

A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.