Tile-Based De-Interleaving for Burst-Efficient DRAM Access
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Solution Overview
Problem
Digital signal processing systems face inefficiencies due to the varying memory requirements of different real-time data standards, leading to underutilization of dedicated memory devices, particularly in handling row-column interleaved data, where DRAM devices' limitations result in inefficient memory access patterns.
Innovation Solution
A digital signal processing system-on-chip with a transfer engine that performs tile-based interleaving and de-interleaving, dividing the process into two memory transfer stages with non-linear and burst-based address sequences to efficiently utilize DRAM interfaces, allowing for flexible handling of different data standards without the need for dedicated memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dedicated memory device is used for interleaving/de-interleaving to handle different digital television and radio standards, then the system can support multiple standards, but the memory is frequently underutilised because it must be sized for the standard with the largest memory demands
Solution Approach 1:
The memory access operation is segmented into two distinct stages: a first stage that reads data from on-chip memory in a non-linear sequence and writes to DRAM, and a second stage that reads from DRAM using burst linear address sequences and writes back to on-chip memory. This segmentation allows each stage to be optimized independently for its specific access pattern, improving overall memory utilization efficiency while supporting multiple standards.
Solution Approach 2:
The system dynamically switches between different address sequence modes (non-linear for the first stage, burst linear for the second stage) depending on the operational phase. This dynamic adaptation allows the memory interface to efficiently handle varying data patterns required by different digital television and radio standards without requiring dedicated memory for each standard.
2Quantity of substance
If DRAM devices are used for memory storage, then larger capacity is available, but access efficiency is reduced due to limited open pages and overhead cycles needed to open pages
Solution Approach 1:
The first memory transfer stage performs preliminary action by reading data from on-chip memory using a non-linear sequence and pre-positioning it in DRAM before the second stage begins. This preliminary organization of data in DRAM prepares it for efficient burst reading in the second stage, reducing the need for frequent page openings and improving access efficiency.
Solution Approach 2:
The system changes the address sequence parameter between stages: the first stage uses a non-linear address sequence optimized for reading interleaved data from on-chip memory, while the second stage uses burst linear address sequences optimized for reading from DRAM. This parameter change adapts the memory access pattern to match the characteristics of each memory type, improving overall efficiency.
3Productivity
If dedicated memory is allocated for each standard to avoid underutilization, then memory utilization is optimized for each standard, but the system complexity and silicon area increase
Solution Approach 1:
The transfer engine is designed as a universal multi-functional device that can handle data reordering for multiple digital television and radio standards through its two-stage memory transfer mechanism. By using configurable address sequences (non-linear for stage one, burst linear for stage two), a single transfer engine can serve multiple standards without requiring separate dedicated memory devices for each standard, thus reducing system complexity while maintaining efficient memory utilization.
Data Source
AI summary
Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.