Tile-Based De-Interleaving for Burst-Efficient DRAM Access
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Solution Overview
Problem
Digital signal processing systems face inefficiencies due to the underutilization of dedicated memory devices for interleaving and de-interleaving operations, as they need to accommodate the largest memory demands across different standards, leading to significant memory waste and increased chip area and cost.
Innovation Solution
A digital signal processing system-on-chip with a transfer engine that performs tile-based interleaving and de-interleaving, utilizing a shared on-chip memory and DRAM, where data is reordered using non-linear and burst sequences to efficiently utilize DRAM interfaces, reducing the need for dedicated memory and optimizing memory access patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the dedicated memory device is sized to handle the standard with the largest memory demands, then all standards can be supported, but significant memory is underutilised and chip area increases
Solution Approach 1:
The memory system is segmented into multiple memory banks that can be independently configured. Each bank can be allocated to different standards as needed, allowing the system to support multiple standards simultaneously without requiring a single large dedicated memory for each standard. This segmentation enables efficient memory utilization while maintaining versatility across different digital standards.
Solution Approach 2:
The memory device is designed with universal functionality to serve multiple digital standards through configurable memory banks. Rather than having separate dedicated memory for each standard, a single universal memory system can be dynamically allocated to handle different standards' requirements, eliminating underutilization while maintaining support for all standards.
2Productivity
If dedicated memory is used for interleaving/de-interleaving operations, then real-time processing is enabled, but memory requirements and chip area increase
Solution Approach 1:
The interleaving/de-interleaving function is merged with the existing memory system rather than using separate dedicated memory. The memory banks are configured to perform both storage and interleaving operations, eliminating the need for additional dedicated memory while maintaining real-time processing capability through efficient memory access patterns.
Solution Approach 2:
The memory system employs dynamic configuration where memory banks can be programmatically allocated and reconfigured based on the specific standard and processing requirements. This dynamic approach allows the same physical memory to adapt to different interleaving depths and patterns, reducing overall memory requirements while maintaining real-time processing performance.
Data Source
AI summary
Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.