Tile-Based GPU Memory Allocation for Multi-Processor Graphics

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Solution Overview

Problem

Graphics processing systems with multiple GPUs face increased memory footprint issues due to multisampling and supersampling, leading to performance degradations and scalability limitations.

Innovation Solution

The method involves determining and allocating memory areas in local memory of each GPU based on the aggregate size of assigned tiles, allowing only the necessary memory to be used for processing, and storing tiles in these allocated areas, thereby reducing memory footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multisampling or super sampling is used, then processing quality is improved, but memory footprint is significantly increased

Engineering Contradiction:
Improveprocessing qualityVSAvoidmemory footprint
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The frame is divided into multiple tiles that are distributed across different GPUs. Each GPU processes only the tiles assigned to it, so the memory footprint on each GPU is reduced from the full frame size to only the size of its assigned tiles. This segmentation allows multisampling to be used for high processing quality while distributing the memory burden across multiple devices.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple GPUs are used to process alternate frames, then processing throughput is improved, but memory management complexity is increased

Engineering Contradiction:
Improveprocessing throughputVSAvoidmemory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The frame processing task is segmented and distributed across multiple GPUs, with each GPU responsible for specific tiles. This allows alternate frames to be processed in parallel, improving throughput. The memory management is simplified by assigning specific memory regions to each GPU based on its tile assignments, avoiding the complexity of managing the entire frame memory across multiple devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system determines the tile assignment and allocates memory areas in advance before processing begins. This preliminary action establishes clear memory boundaries and responsibilities for each GPU, simplifying the memory management process during parallel frame processing and enabling efficient throughput.

Inventive Principle:
Principle #10Preliminary action

3Speed

If the same frame is distributed to multiple GPUs for concurrent processing, then processing speed is improved, but memory footprint per GPU is increased

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory footprint per GPU
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The frame is segmented into tiles and distributed to multiple GPUs, with each GPU receiving only the tiles it needs to process. This segmentation enables concurrent processing of the same frame at high speed while each GPU maintains a reduced memory footprint corresponding to only its assigned tiles rather than the full frame.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8963931B2Tiling compaction in multi-processor systems
Publication Date: 2015.02.24 ADVANCED MICRO DEVICES INC
  • US8963931B2 patent drawing
  • US8963931B2 patent drawing
  • US8963931B2 patent drawing

AI summary

A method and system for processing a graphics frame in a multi-processor computing environment are described. Embodiments of the present invention enable the reduction of the memory footprint required for processing a graphics frame in a multi-processor system. In one embodiment a method of processing a graphics frame using a plurality of processors is presented. The method includes determining a respective assignment of tiles of the graphics frame to each processor of the plurality of processors; allocating a memory area in a local memory of each processor, where the size of the allocated memory area substantially corresponds to the aggregate size of tiles assigned to the respective processor; and storing the tiles of the respective assignment of tiles in the memory area of each respective processor.