Tile-Based Interleaving Engine for Row-Column Data Reordering
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Solution Overview
Problem
Digital signal processing systems face inefficiencies due to the varying memory requirements of different real-time data standards, leading to underutilization of dedicated memory devices, particularly in handling row-column interleaved data, where DRAM devices' limited page access efficiency results in overhead cycles and inefficient data access patterns.
Innovation Solution
A digital signal processing system-on-chip with a transfer engine that performs tile-based interleaving and de-interleaving, dividing the process into two memory transfer stages: one from on-chip memory to DRAM and another from DRAM back to on-chip memory, using non-linear and burst sequences to optimize data reordering and efficiently utilize DRAM interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dedicated memory device is used for interleaving/de-interleaving to handle different digital television and radio standards, then the system can support multiple standards, but the memory is frequently underutilised because it must be sized for the standard with the largest memory demands
Solution Approach 1:
The patent divides the dedicated interleaving memory into multiple smaller on-chip memory banks. Each bank can be independently configured and used for different standards, allowing the system to allocate only the necessary memory capacity for the currently active standard rather than provisioning for the maximum possible demand across all standards.
Solution Approach 2:
The on-chip memory banks are designed to be multi-functional, serving both as general-purpose data storage and as dedicated interleaving memory. The memory architecture allows dynamic reconfiguration to support different interleaving patterns and sizes required by various digital television and radio standards, eliminating the need for separate dedicated memory for each standard.
2Quantity of substance
If DRAM devices are used for memory-intensive interleaving operations, then large capacity is available, but access efficiency is reduced due to limited page open capability and overhead cycles
Solution Approach 1:
The system pre-loads required data blocks into on-chip memory banks before interleaving operations begin. By having data readily available in on-chip memory rather than fetching from DRAM during the actual interleaving process, the system eliminates DRAM page open overhead and achieves continuous high-speed access during critical processing intervals.
Solution Approach 2:
The on-chip memory banks serve as an intermediary buffer between DRAM and the interleaving processing logic. Data is transferred from DRAM to on-chip memory in advance, and the interleaving operation operates on this intermediate storage, thereby decoupling the slow DRAM access characteristics from the fast interleaving processing requirements.
3Productivity
If dedicated hardware peripherals are used for rapid interleaving operations, then processing speed is improved, but chip area and cost increase
Solution Approach 1:
The patent combines the interleaving processing function with the existing on-chip memory subsystem rather than implementing it as a separate dedicated hardware peripheral. The memory controller and address generation logic are enhanced to perform interleaving patterns directly during memory access operations, merging two functions into a single integrated implementation that reduces overall chip area.
Solution Approach 2:
The on-chip memory system is enhanced to perform interleaving operations autonomously during data transfer operations. By integrating interleaving capability into the memory subsystem itself, the system eliminates the need for separate dedicated interleaving hardware while maintaining rapid processing speeds through efficient use of existing memory infrastructure.
Data Source
AI summary
Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.