Tile-Level Predication for Machine Perception Integrated Circuits
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Solution Overview
Problem
Modern GPUs lack optimization for handling complex machine learning algorithms used in machine perception technologies, leading to inefficiencies in processing sensor data for autonomous robotics and vehicles, which requires advanced and real-time computing capabilities.
Innovation Solution
The implementation of a tile-level predication method in integrated circuit architecture, where predicate state values from multiple processing cores are summed and propagated to an instructions generating circuit to optimize instruction execution, allowing for efficient branching and loop exit decisions, thereby enhancing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If general purpose integrated circuits including CPUs and GPUs are used for processing sensor data, then the system can handle basic computations, but the processing speed and efficiency are insufficient for real-time machine learning algorithms
Solution Approach 1:
The processing system is divided into multiple computing tiles, each containing multiple processing cores. This segmentation allows parallel processing of sensor data across multiple tiles and cores simultaneously, significantly increasing processing throughput while maintaining manageable complexity through modular design.
Solution Approach 2:
The system dynamically adjusts the number of active processing cores based on workload demands and predicate conditions. Processing cores can be activated or deactivated on-the-fly, allowing the system to optimize performance for different computational tasks without requiring a permanently over-provisioned complex architecture.
2Adaptability or versatility
If additional and disparate circuitry is assembled to a traditional GPU to handle path planning and sensor fusion, then the perception processing capabilities are enhanced, but computational inefficiencies and fragmentation occur
Solution Approach 1:
Each computing tile is designed as a universal processing unit capable of executing multiple types of algorithms including neural networks, path planning, and sensor fusion. The same hardware infrastructure supports diverse perception tasks through software configuration rather than requiring specialized disparate circuitry for each function.
Solution Approach 2:
The patent combines multiple perception processing functions (sensor data processing, machine learning inference, path planning, sensor fusion) into a single integrated computing system. This consolidation eliminates the fragmentation and inefficiencies of assembling disparate circuitry, while maintaining the versatility to handle all perception tasks through unified resource management.
3Reliability
If predicate state values are evaluated for each processing core individually, then accurate branching decisions can be made, but the overhead of collecting and summing predicate values across multiple cores increases processing time
Solution Approach 1:
Predicate state values are evaluated and collected in advance during the execution pipeline, before final branching decisions are made. This preliminary evaluation allows the system to prepare branching information proactively, reducing the time penalty of individual core evaluation by overlapping predicate collection with other processing operations.
Solution Approach 2:
The system maintains continuous evaluation of predicate states across all processing cores throughout the execution pipeline, rather than performing discrete batch evaluations. This continuous monitoring allows branching decisions to be made based on accumulated predicate information without interrupting the flow of computation, minimizing time loss while maintaining accurate branching control.
Data Source
AI summary
Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.