Tile Mapping Compilation Method for Parallel Processing

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Solution Overview

Problem

Existing tools for parallel processing systems do not effectively balance the data exchange cost between tiles, leading to inefficient processing and memory burden distribution across parallel resources.

Innovation Solution

A method and tool that automatically migrates portions of code between tiles to reduce data exchange by determining and adapting subgraphs based on heuristic rules, such as limiting the number of tiles spanned and ensuring data nodes and compute vertices are allocated optimally, thereby reducing exchange delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data nodes and compute vertices are distributed across multiple tiles to enable parallel processing, then processing throughput is improved, but data exchange cost between tiles increases

Engineering Contradiction:
Improveprocessing throughputVSAvoiddata exchange delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the graph computation into subgraphs that can be independently executed on different tiles. By dividing the overall computation graph into smaller subgraphs and assigning them to different tiles, the system achieves parallel processing while controlling inter-tile data exchange through the use of intermediate results storage and retrieval mechanisms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs copying of data nodes and compute vertices across multiple tiles to eliminate or reduce data exchange operations. When a data node or compute vertex is copied to multiple tiles, the need for inter-tile communication is reduced, as each tile can operate independently on its local copy, thereby improving processing throughput while minimizing data exchange delays.

Inventive Principle:
Principle #26Copying

2Loss of time

If code is migrated between tiles to reduce data exchange, then data exchange cost is reduced, but system complexity increases

Engineering Contradiction:
Improvedata exchange delayVSAvoidtile migration complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent performs preliminary analysis of the computation graph to identify data nodes and compute vertices that would benefit from migration. By pre-determining which elements should be copied to which tiles based on data access patterns and computation dependencies, the system reduces runtime complexity while achieving optimal data distribution. This preliminary planning phase enables the system to minimize data exchange without requiring complex runtime migration decisions.

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If data nodes and compute vertices are concentrated on fewer tiles, then data exchange is reduced, but parallel processing capability decreases

Engineering Contradiction:
Improvedata exchange delayVSAvoidparallel processing throughput
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent implements dynamic allocation of data nodes and compute vertices to tiles based on runtime conditions and data access patterns. Rather than using a static distribution scheme, the system can adaptively determine the optimal placement of computational elements, allowing it to balance between reducing data exchange and maintaining parallel processing capability. This dynamic approach enables the system to optimize for both throughput and communication efficiency depending on the specific computation workload.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11366649B2Compilation method
Publication Date: 2022.06.21 GRAPHCORE LTD
  • US11366649B2 patent drawing
  • US11366649B2 patent drawing
  • US11366649B2 patent drawing

AI summary

A method for generating a program to run on multiple tiles. The method comprises: receiving an input graph comprising data nodes, compute vertices and edges; receiving an initial tile-mapping specifying which data nodes and vertices are allocated to which tile; and determining a subgraph of the input graph that meets one or more heuristic rules. The rules comprises: the subgraph comprises at least one data node, the subgraph spans no more than a threshold number of tiles in the initial tile-mapping, and the subgraph comprises at least a minimum number of edges outputting to one or more vertices on one or more other tiles. The method further comprises adapting the initial mapping to migrate the data nodes and any vertices of the determined subgraph to said one or more other tiles.