Tile Based Precision Rasterization for GPU Performance

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Solution Overview

Problem

Prior art 3-D rendering architectures struggle to scale with increasingly complex scenes and large screen resolutions, leading to bottlenecks in rasterization processes, which results in inadequate performance and increased power consumption or reduced fabrication yield when attempting to enhance rendering capabilities.

Innovation Solution

Implementing a tile-based precision rasterization method in the graphics processor, where graphics primitives are rasterized at a higher precision to generate tiles, which are then rasterized at a lower precision to output covered pixels, efficiently utilizing GPU resources and scaling to large screen sizes while maintaining real-time performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If prior art rasterization solutions use line-by-line stepping and per pixel evaluation to handle large screen resolutions, then coverage of all pixels within primitives is achieved, but rasterization resources require increasingly larger resources leading to bottlenecks in 3-D rendering performance

Engineering Contradiction:
Improvepixel coverage accuracyVSAvoidrendering performance
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent divides the screen into multiple tiles, where each tile is a smaller subset of pixels. The rasterization process first determines tile coverage at a coarser level, then processes individual pixels within covered tiles. This segmentation reduces the computational burden by breaking down the large-scale per-pixel evaluation into smaller, more manageable tile-level operations followed by selective pixel-level processing only in regions that need it.

Inventive Principle:
Principle #1Segmentation

2Speed

If GPU clock speed is increased to handle larger screen sizes and maintain real-time rendering performance, then rendering speed is improved, but power consumption and heat production increase

Engineering Contradiction:
Improverendering speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by performing full precision rasterization only for tiles that are actually covered by primitives, rather than processing every pixel on the entire screen at full precision. The tile-based approach allows the system to perform coarser evaluation for tile coverage and then apply finer pixel-level processing only where necessary, reducing overall computational workload and energy consumption while maintaining rendering quality in visible regions.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If large numbers of parallel execution units are incorporated to increase 3-D rendering performance, then processing capacity is improved, but integrated circuit die size increases and fabrication yield decreases

Engineering Contradiction:
Improverendering performanceVSAvoiddie size
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a new dimensional organization by adding the tile dimension between screen and pixel levels. Instead of directly processing pixels in a traditional rasterization pipeline, the system adds tile-level processing as an intermediate layer. This dimensional change allows the same hardware resources to handle larger screens more efficiently by organizing work in tile-based units, reducing the need for proportionally more parallel execution units.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Measurement precision

If integer precision is increased to address larger numbers of pixels on high-resolution displays, then pixel addressing capability is improved, but silicon area requirements increase

Engineering Contradiction:
Improvepixel addressing precisionVSAvoidsilicon area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent applies local quality by using different precision levels for different parts of the processing pipeline. Tile-level operations use coarser precision since tiles are smaller subsets of the full screen, while pixel-level operations within covered tiles use finer precision. This localized precision approach allows the system to maintain high pixel addressing capability where needed while using reduced precision for broader tile coverage calculations, thereby reducing overall silicon area requirements for precision-related hardware.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9070213B2Tile based precision rasterization in a graphics pipeline
Publication Date: 2015.06.30 NVIDIA CORP
  • US9070213B2 patent drawing
  • US9070213B2 patent drawing
  • US9070213B2 patent drawing

AI summary

In a raster stage of a graphics processor, a method for tile based precision rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive at a first level precision to generate a plurality of tiles of pixels. The tiles are then rasterized at a second level precision to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.