Switch-Interconnected Tile Processors for Reconfigurable Parallel Computing
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Solution Overview
Problem
The high cost and power inefficiency of Field Programmable Gate Arrays (FPGAs) compared to Application Specific Integrated Circuits (ASICs) hinder their widespread adoption in parallel processing environments, despite FPGAs' reconfigurability and ability to adapt to changing protocols.
Innovation Solution
A tiled integrated circuit architecture featuring pipelined processors with switching circuitry that forwards data between tiles, enabling efficient parallel processing and reconfigurable logic units, which allows for higher processing power and flexible memory access without the need for frequent reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used for reconfigurable logic, then adaptability is improved, but power consumption increases and performance decreases
Solution Approach 1:
The system is divided into multiple independent tiles, each containing its own reconfigurable logic units. This segmentation allows only the necessary portions of the circuit to be reconfigured for a given task, rather than reconfiguring the entire FPGA, thereby reducing power consumption while maintaining adaptability.
Solution Approach 2:
The reconfigurable logic units within each tile can dynamically change their configuration to adapt to different computational tasks. This dynamic reconfiguration capability provides the adaptability of FPGAs while the localized scope of reconfiguration reduces the overall power consumption compared to full-FPGA reconfiguration.
2Adaptability or versatility
If FPGAs are used for reconfigurable logic, then adaptability is improved, but processing performance worsens
Solution Approach 1:
By segmenting the processing system into multiple tiles with dedicated reconfigurable logic units, each tile can independently process data in parallel. This segmentation enables the system to achieve ASIC-like performance for specific tasks while retaining FPGA-like reconfigurability, as each tile can be optimized for its specific function.
Solution Approach 2:
The invention merges the reconfigurable logic units with fixed-function processing elements within each tile, creating a hybrid architecture. This merging allows the system to combine the adaptability of reconfigurable logic with the high performance of fixed-function circuits, achieving both goals simultaneously.
3Productivity
If ASICs are used for fixed functionality, then processing performance is improved, but adaptability worsens
Solution Approach 1:
Each tile in the array contains reconfigurable logic units that can dynamically change their configuration to adapt to different computational tasks. This dynamic capability provides the adaptability that traditional ASICs lack, while the overall array architecture maintains high processing performance through parallel execution across multiple tiles.
4Productivity
If tiled architecture with switching circuitry is implemented, then processing power is improved, but device complexity increases
Solution Approach 1:
The switching circuitry within each tile is designed to be universal, capable of routing data to multiple different destinations and supporting various communication patterns. This universality reduces the overall complexity by using a single versatile switching mechanism rather than dedicated routing logic for each possible connection, while still enabling high processing power through efficient data movement.
Data Source
AI summary
An integrated circuit includes a plurality of tiles. Each tile includes a pipelined processor configured to process multiple streams of instructions for the processor; and a switch including switching circuitry to forward data over data paths from other tiles to one or more pipeline stages of the processor and to switches of other tiles. At least some of the data is forwarded based on one or more streams of instructions for the switch.