Tile-to-Raster Conversion Using Virtual Square Tile Buffers

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Solution Overview

Problem

Existing image processing systems using Deep-Learning Neural Networks require additional Static Random-Access Memory (SRAM) for temporary data storage during Tile to Raster (T2R) conversion due to the use of ping-pong buffers, leading to increased storage costs and resource consumption.

Innovation Solution

A method and system for T2R conversion that segments input data into virtual square tiles in both spatial and storage domains, utilizing a hardware accelerator with a single port memory to reduce SRAM requirements by prioritizing read operations over write operations, thereby optimizing storage efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a ping-pong buffer is used for T2R conversion, then data flow continuity is maintained, but SRAM storage area requirement increases

Engineering Contradiction:
Improvedata flow continuityVSAvoidSRAM storage area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the tile buffer into multiple virtual square tiles in both spatial and storage domains. This segmentation allows the system to process and transfer data in smaller chunks through multiple channels, maintaining continuous data flow while utilizing the same SRAM area more efficiently without requiring duplicate buffer storage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of processing by organizing tile data into virtual square tiles with row-major and column-major ordering. This dimensional reorganization enables simultaneous read and write operations across different tile segments, maintaining data flow continuity while eliminating the need for ping-pong buffer duplication.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If additional SRAM is allocated for T2R conversion, then storage capacity increases, but system cost increases

Engineering Contradiction:
Improvestorage capacityVSAvoidsystem cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent merges the functions of multiple tile buffers into a single shared tile buffer structure. By consolidating buffer resources and managing them through virtual square tile segmentation, the system achieves the same storage capacity without requiring additional SRAM allocation, thereby reducing system cost.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared tile buffer is designed to serve multiple purposes through virtual square tile organization. The same buffer memory is universally used for both spatial and storage domain operations, eliminating the need for dedicated separate buffers and reducing overall SRAM requirements while maintaining full storage capacity functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If ping-pong buffer is implemented, then data transfer reliability improves, but device complexity increases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidbuffer management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The virtual square tile segmentation enables self-service data management where the buffer automatically organizes and manages data flow through its structured layout. The row-major and column-major ordering of virtual tiles provides inherent data routing and transfer management, reducing the need for complex external buffer control logic while maintaining reliable data transfer.

Inventive Principle:
Principle #25Self-service

4Quantity of substance

If SRAM area is reduced, then storage efficiency improves, but data flow continuity may be affected

Engineering Contradiction:
Improvestorage efficiencyVSAvoiddata flow continuity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the limited SRAM area into multiple virtual square tiles that can be independently managed. This segmentation allows efficient utilization of available storage space while maintaining multiple active data channels, ensuring continuous data flow even with reduced total SRAM area by processing data through different tile segments in parallel or sequence.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12511704B2Method for performing tile to raster (T2R) conversion in deep learning hardware accelerator
Publication Date: 2025.12.30 SAMSUNG ELECTRONICS CO LTD
  • US12511704B2 patent drawing
  • US12511704B2 patent drawing
  • US12511704B2 patent drawing

AI summary

A method for performing Tile to Raster (T2R) conversion includes: receiving tile input data including a stream of a plurality of tiles each having a tile height, a tile input width, a macroblock width (MBW), and data bits; segmenting the tile input data based on a total number of virtual square tiles; segmenting a Tile Buffer (TB) into one or more of the virtual square tiles based on the received tile input data; and performing a raster-scanning operation on each of the segmented tile input data and the segmented TB based on the total number of virtual square tiles to generate raster data.