Tile-Based Primitive Rendering With Lane Masks for Lower GPU Memory Traffic
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Solution Overview
Problem
The power consumption of Immediate-Mode-Rendering (IMR) architecture in GPUs is high due to frequent system memory access, and current API designs are not adapted to Tile-Based-Rendering (TBR) architecture, requiring complex hardware design and driver dispatch.
Innovation Solution
A method and apparatus that tiles primitives based on received information, caches them in on-chip memory, and renders when a preset condition is met, reducing the need for frequent system memory interaction and adapting to existing API designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Immediate-Mode-Rendering (IMR) architecture is used, then rendering speed and simplicity are improved, but power consumption increases due to frequent system memory access
Solution Approach 1:
The patent divides the screen into multiple tiles and processes primitives in a tile-by-tile manner. Each tile is rendered independently using on-chip memory, segmenting the rendering workload to reduce system memory access frequency while maintaining rendering throughput
Solution Approach 2:
The patent performs preliminary tiling of primitives and stores tile-based information in on-chip memory before actual rendering. This preliminary organization of data by tile allows the rendering stage to operate with localized data, reducing the need for frequent system memory access during power-intensive operations
2Use of energy by moving object
If Tile-Based-Rendering (TBR) architecture is used, then power consumption is reduced, but hardware complexity and driver dispatch requirements increase
Solution Approach 1:
The patent maintains compatibility with existing OpenGL and Direct3D APIs, allowing the TBR architecture to handle multiple rendering workflows through a unified interface. The tile-based rendering logic is integrated into the existing rendering pipeline, enabling one hardware design to serve both IMR and TBR modes without requiring separate dedicated hardware for each architecture
Solution Approach 2:
The patent introduces a tile-based information structure as an intermediary between the primitive setup stage and the rendering stage. This intermediate representation organizes primitive data by tile coordinates and attributes, serving as a bridge that allows standard APIs to work with tile-based rendering without requiring complex driver translation layers
3Loss of energy
If Tile-Based-Rendering (TBR) architecture is used, then system memory access frequency is reduced, but API compatibility and driver dispatch complexity increase
Solution Approach 1:
The patent implements a dynamic rendering approach where the rendering pipeline can adapt between immediate-mode and tile-based modes depending on the workload and hardware capabilities. The system dynamically organizes primitives into tiles when beneficial, while maintaining the ability to process primitives in traditional order when API requirements demand, providing flexibility without sacrificing memory efficiency
Data Source
AI summary
Disclosed are a primitive rendering method and apparatus, a computer device, and a storage medium. The method includes: receiving primitive information, determining a target tile in which a primitive is located according to the primitive information, obtaining tile-based information corresponding to the primitive; buffering the primitive information and the tile-based information; when a preset condition is satisfied, rendering a primitive in each target tile according to the primitive information and the tile-based information. With the present disclosure, there is no need to frequently exchange the color information with the system memory, and this is also no need to exchange the primitive tile-based information with the system memory, thereby effectively reducing the data interaction between the on-chip data of the GPU and the system memory.