Tile-Switch Mapping Architecture for On-Chip Bus Energy Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional tile-switch mapping methods in on-chip bus architectures do not effectively minimize energy consumption and communication delay time due to their focus on one-to-one mapping and lack of optimization for hop distance reduction between cores in mesh-based systems.
Innovation Solution
An optimized tile-switch mapping method that calculates and multiplies data communication flows by hop distance values and communication volumes to determine the mapping relationship between cores and tiles, minimizing the average hop distance and energy consumption by adjusting proximity index values and link bandwidths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional one-to-one tile-switch mapping is used, then the mapping architecture is simple, but the energy consumption and communication delay time are high due to increased hop distance between cores
Solution Approach 1:
The patent changes the mapping parameter from simple one-to-one correspondence to an optimized many-to-one mapping relationship. By calculating communication volumes and hop distances between all core pairs, the system determines which multiple tiles should map to the same switch to minimize total communication cost, thereby reducing energy consumption without excessive complexity increase
Solution Approach 2:
The patent performs preliminary calculation of communication volumes and hop distances during the design phase. By pre-computing the optimal tile-switch mapping based on expected communication patterns, the system avoids suboptimal mappings that would result in higher energy consumption during actual operation
2Device complexity
If conventional one-to-one tile-switch mapping is used, then the mapping architecture is simple, but the communication delay time is high due to increased hop distance between cores
Solution Approach 1:
The patent optimizes the mapping parameter by considering both communication volume and hop distance simultaneously. By changing from simple sequential mapping to an optimized mapping that groups tiles with high communication frequency to the same or nearby switches, the system reduces the average hop distance and thus communication delay time
Solution Approach 2:
The patent creates multiple virtual mapping configurations and evaluates them to find the optimal mapping. By considering alternative mapping schemes and selecting the one that minimizes total communication delay, the system achieves better performance without permanently increasing physical complexity
3Use of energy by moving object
If optimized tile-switch mapping is implemented, then energy consumption and communication delay time are reduced, but the calculation complexity and design time are increased
Solution Approach 1:
The patent segments the optimization problem into manageable parts: first calculating communication volumes between core pairs, then determining hop distances for different mapping configurations, and finally combining these factors to determine optimal mappings. This segmented approach makes the complex optimization problem solvable through systematic calculation
Solution Approach 2:
The patent introduces communication volume as an intermediary parameter that mediates between physical tile positions and logical switch connections. By using this intermediary metric, the system can optimize energy consumption and delay time without directly managing the complex many-to-one mapping relationships
4Loss of time
If optimized tile-switch mapping is implemented, then communication delay time is reduced, but the calculation complexity and design time are increased
Solution Approach 1:
The patent divides the delay time optimization into separate calculable components: communication volume between cores, hop distance for each mapping configuration, and weighted combination of these factors. This segmentation allows systematic optimization of communication delay without overwhelming design complexity
Solution Approach 2:
The patent performs preliminary optimization calculations during the design phase to establish the optimal tile-switch mapping. By pre-determining the mapping that minimizes communication delay based on expected workloads, the system avoids runtime optimization complexity while achieving minimal delay time
Data Source
AI summary
Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the hop distance between cores when the mapping relationship between cores and tiles is determined, to thereby minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the method of creating a tile-switch mapping architecture presents a standard for comparing the optimization of other mapping architectures.