Tile Synchronization Logic for Exception Handling in Multi-Tile Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging and inspecting multitile, multithreaded processor architectures are challenging due to the complexity of dependencies between tiles and the need for efficient synchronization mechanisms, particularly in bulk synchronous parallel (BSP) communication schemes where all tiles must complete a compute phase before proceeding to an exchange phase.
Innovation Solution
A processing system with an interconnect that implements a bulk synchronous parallel scheme, where each tile performs a compute phase followed by an exchange phase, with synchronization logic to ensure all tiles complete the compute phase before proceeding, and debug interfaces for exception handling and resolution, allowing tiles in an excepted state to pause instruction issuance until the exception is resolved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all tiles must complete compute phase before proceeding to exchange phase (BSP synchronization), then data consistency between tiles is improved, but processing time and system throughput deteriorate due to waiting for slowest tile
Solution Approach 1:
The patent applies partial synchronization by allowing tiles that have completed their compute phase to proceed to the exchange phase early, rather than waiting for all tiles. This means some tiles perform exchange operations partially before full synchronization is achieved, trading complete synchronization for reduced waiting time and improved throughput.
2Measurement precision
If exception handling pauses all tiles until resolution, then debugging accuracy is improved, but productivity of other tiles deteriorates due to system-wide interruption
Solution Approach 1:
The patent segments the exception handling process by isolating the excepted tile from the synchronization barrier. When a tile raises an exception, only that specific tile is paused and removed from the synchronization group, while other tiles continue to complete their compute phases and proceed to exchange phases without interruption. This localized exception handling maintains debugging accuracy for the affected tile while preserving productivity of unaffected tiles.
3Difficulty of detecting and measuring
If exception is raised during compute phase, then exception detection is improved, but synchronization complexity increases due to need to track excepted tiles
Solution Approach 1:
The patent introduces an intermediary exception handling mechanism that mediates between exception detection and synchronization control. When a tile raises an exception, the intermediary mechanism tracks the excepted tile's state and automatically adjusts synchronization behavior, preventing the exception from propagating to other tiles while maintaining proper synchronization for non-affected tiles. This intermediary layer simplifies the overall synchronization logic by centralizing exception management.
Data Source
AI summary
A multitile processing system has an execution unit on each tile, and an interconnect which conducts communications between the tiles according to a bulk synchronous parallel scheme. Each tile performs an on-tile compute phase followed by an intertile exchange phase, where the exchange phase is held back until all tiles in a particular group have completed the compute phase. On completion of the compute phase, each tile generates a synchronisation request and pauses an issue of instructions until it receives a synchronisation acknowledgement. If a tile attains an excepted state, it raises an exception signal and pauses instruction issue until the excepted state has been resolved. However, tiles which are not in the excepted state can continue to perform their on-tile computer phase, and will issue their own synchronisation request in their own normal time frame. Synchronisation acknowledgements will not be received from all of the tiles in the group until the excepted state has been resolved on the tile with the excepted state.