Tile Synchronization Logic for Multi-Tile Processing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In multi-tile processing arrangements, existing technologies face challenges in synchronizing workloads across multiple tiles efficiently, particularly in bulk synchronous parallel (BSP) communication schemes, where all tiles must complete a compute phase before proceeding to an exchange phase, leading to potential bottlenecks and inefficiencies.

Innovation Solution

A processor architecture with a dedicated instruction set that includes a synchronization instruction and an abstain instruction, allowing tiles to opt out of the barrier synchronization, enabling some tiles to continue processing while others wait, and automatic synchronization mechanisms to manage synchronization requests and acknowledgments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If barrier synchronization is implemented to ensure all tiles complete compute phase before exchange phase, then data consistency and correctness are improved, but processing throughput and efficiency deteriorate due to tiles waiting at synchronization barriers

Engineering Contradiction:

Improvedata consistencyVSAvoidprocessing throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamics by making the synchronization barrier configurable rather than fixed. The system can dynamically adjust between synchronized and asynchronous operation modes based on workload characteristics. Tiles can selectively participate in synchronization barriers through configuration bits, allowing the system to adapt its synchronization behavior to optimize for either correctness or throughput depending on the specific computational task at hand.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of synchronization participation by introducing configuration mechanisms that allow tiles to opt-in or opt-out of barriers. This parameter change enables the system to transition from mandatory synchronization (ensuring correctness) to selective or optional synchronization (improving throughput), thereby resolving the contradiction between reliability and productivity.

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If all tiles must wait at synchronization barriers, then coordination between tiles is simplified, but wait times increase and processing efficiency decreases

Engineering Contradiction:

Improvecoordination simplicityVSAvoidwait time

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The patent segments the synchronization requirement by allowing different tiles to have different synchronization participation levels. Instead of a monolithic barrier that all tiles must cross, the system divides synchronization into optional participation, enabling tiles that have completed their work to proceed without waiting for others, thereby reducing wait time while maintaining coordination where needed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by implementing selective synchronization where only necessary tiles participate in barriers. This partial participation reduces the coordination overhead and wait times for tiles that don't need to synchronize, while still maintaining the coordination simplicity for those that do require it.

Inventive Principle:

Principle #16Partial or excessive action

3Stability of the object's composition

If synchronous barrier synchronization is used, then all tiles are guaranteed to be at the same execution point, but tiles with completed work cannot proceed and resource utilization decreases

Engineering Contradiction:

Improveexecution state uniformityVSAvoidresource utilization

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent introduces dynamics to the execution state uniformity by allowing tiles to transition between synchronized and asynchronous states based on their individual completion status. Configuration mechanisms enable tiles to dynamically opt-out of barriers when their work is complete, allowing them to proceed independently while maintaining execution state uniformity for tiles that remain synchronized.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent ensures continuity of useful action by allowing tiles to continue processing and executing subsequent instructions immediately upon completing their compute phase, without being blocked by synchronization barriers. This continuous execution improves resource utilization while configuration options maintain execution state uniformity when required by the algorithm.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS10628377B2Synchronization in a multi-tile processing arrangement

Publication Date: 2020.04.21 GRAPHCORE LTD

AI summary

A processing system comprising an arrangement of tiles and synchronization logic in the form of hardware logic for coordinating between a group of some or all of said tiles. The instruction set comprises a synchronization instruction which causes an instance of a synchronization request to be transmitted from the respective tile to the synchronization logic, and suspends instruction issue on the respective tile pending a synchronization acknowledgement. In response to receiving an instance of the synchronization request from all of the tiles of the group, the synchronization logic returns the synchronization acknowledgment back to each of the tiles in the group to allow the instruction issue to resume. The instruction set further comprises an abstain instruction, which sends an instance of the synchronization request but does not suspend instruction issue on the respective tile pending the synchronization acknowledgement, instead allowing the instruction issue on the respective tile to continue.