Tileable Crossbar Switch with Pipeline Delay Registers
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Solution Overview
Problem
Existing crossbar switches face challenges in implementing high-density designs in application-specific integrated circuits (ASIC) and system-on-a-chip (SoC) due to combinatorial topologies leading to wiring congestion and uneven distribution of inputs and outputs, which are not systematically addressed by current technologies.
Innovation Solution
A tileable crossbar architecture is introduced, comprising abutted tiles with edge and middle tiles, where each tile includes pipeline delay registers to enable data signal direction change and even distribution of inputs and outputs, reducing wiring congestion and enforcing pipelining across the switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a combinatorial topology is used in existing crossbar switches, then the switch can be implemented with simpler architecture, but wiring congestion occurs and inputs/outputs are unevenly distributed
Solution Approach 1:
The crossbar switch is divided into multiple tiles, each handling a subset of inputs and outputs. This segmentation distributes the wiring load across different spatial regions, eliminating the wiring congestion that occurs in monolithic combinatorial designs while maintaining architectural simplicity through modular repetition.
2Quantity of substance
If high-density crossbar switches are implemented in ASIC/SoC, then switching capacity increases, but wiring congestion and uneven input/output distribution worsen
Solution Approach 1:
High-density switching capacity is achieved by tiling multiple modular units throughout the ASIC/SoC substrate. Each tile independently manages local wiring, preventing congestion even as overall capacity scales. The segmented architecture allows dense packing without the wiring conflicts inherent in monolithic high-capacity designs.
Solution Approach 2:
The crossbar switch transitions from a planar 2D combinatorial layout to a 3D tiled architecture where multiple layers of switching fabric are stacked and interconnected. This dimensional transition allows high-density connectivity while distributing wiring across vertical and horizontal dimensions, eliminating congestion in any single plane.
3Device complexity
If inputs are concentrated on one edge and outputs on another edge, then the switch structure is simplified, but inputs and outputs are unevenly distributed causing routing inefficiency
Solution Approach 1:
Each tile within the crossbar switch employs asymmetric input/output placement optimized for its specific position in the tile array. Edge tiles have I/O ports configured to match their boundary positions, while internal tiles have symmetric bidirectional ports. This controlled asymmetry achieves even overall distribution across the switch while maintaining simple local structures.
4Adaptability or versatility
If pipeline delay registers are added to enable direction change, then routing flexibility improves, but device complexity increases
Solution Approach 1:
Pipeline delay registers are designed as universal multi-functional elements that simultaneously provide data buffering, direction changing, and synchronization across all tiles. This single versatile component achieves routing flexibility without requiring separate specialized circuits for each function, thereby limiting the increase in overall device complexity.
Data Source
AI summary
Examples herein relate to crossbar switches and related circuitry. An example crossbar switch includes a plurality of abutted tiles forming a crossbar. The plurality of abutted tiles includes a plurality of edge tiles and at least one middle tile, where each side of each middle tile abuts an edge tile or another middle tile. Each middle tile includes data inputs connected to data outputs, switched data inputs connected to switched data outputs, and pipeline delay registers coupled to data inputs and switched data outputs to allow transmission of a data signal to change directions inside each middle tile. Each edge tile includes a crossbar input, a crossbar output, and a set of inputs, outputs, and pipeline delay registers to allow transmission of data signals from any side of the edge tile to any other side of the edge tile.