Tiled 3D Array Storage for Stencil Calculation Performance
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Solution Overview
Problem
Inefficient data retrieval in 3D stencil calculations due to the non-contiguous storage of adjacent cells across planes in 3D arrays, leading to frequent page and TLB misses, which cause significant delays and reduce the performance of these calculations.
Innovation Solution
Storing data in a tiled manner where adjacent rows across planes are interleaved to fit within a single page, allowing for contiguous storage and reducing the frequency of page and TLB misses, while maintaining compatibility with the original row-column-plane organization through an accessing component that controls the order of data access and performs cache blocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data of a 3D array is stored in a row-column-plane manner with contiguous storage for adjacent cells in the same row, then data access within the same row is efficient, but data access for adjacent cells in adjacent planes incurs significant delays due to page transitions
Solution Approach 1:
The patent applies dimensionality change by transforming the storage organization from a traditional 3D row-column-plane structure to a tiled structure where data from multiple planes are interleaved together. This creates a new dimensional arrangement where adjacent cells across plane boundaries are mapped to contiguous storage locations, effectively adding a tile dimension that spans multiple original planes. The tile organization allows data from adjacent planes to be accessed without page transitions, resolving the speed-time contradiction for cross-plane access patterns.
Solution Approach 2:
The patent segments the 3D array data into smaller tiles, where each tile contains data from multiple planes organized in a contiguous manner. By dividing the large 3D array into manageable tile segments, the patent ensures that each tile fits within a single page, eliminating page transitions during tile access. This segmentation approach allows efficient caching and reduces the page transition delays that occur with traditional row-column-plane storage when accessing adjacent planes.
2Ease of manufacture
If data is stored in traditional row-column-plane organization, then storage layout is simple, but frequent page and TLB misses occur during 3D stencil calculations accessing adjacent planes
Solution Approach 1:
The patent introduces a tile dimension that overlays the traditional row-column-plane organization, creating a multi-dimensional storage view. This additional dimensional layer organizes data into tiles that span multiple planes, allowing the same physical storage to be accessed efficiently for stencil calculations. The tile organization maintains compatibility with the original simple row-column-plane layout while adding the performance benefits of contiguous cross-plane access, thus improving productivity without significantly complicating the storage organization.
3Loss of time
If pages are cached in TLB to reduce access delays, then address translation is faster, but limited TLB storage locations cause repeated evictions and reloads when accessing many different pages
Solution Approach 1:
The patent segments the address space into tile-based units, where each tile contains data from multiple planes organized to fit within a single page. This segmentation reduces the total number of pages that need to be cached in the TLB, as related data that would traditionally span multiple pages is now contained within fewer, larger tiles. By reducing the page count, the TLB can maintain all necessary address translations without frequent evictions, improving access time while simplifying TLB management.
Solution Approach 2:
The patent merges data from multiple planes into unified tiles, where adjacent cells across plane boundaries are stored contiguously within the same page. This merging eliminates the need for separate page translations for each plane, reducing the number of TLB entries required. By combining related data from multiple planes into single-page tiles, the system reduces TLB eviction frequency and the complexity of managing multiple page translations for stencil calculation patterns.
Data Source
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AI summary
Various embodiments are generally directed to storing data of a three-dimensional (3D) array in a tiled manner in which adjacent rows of adjacent planes are interleaved to enable more efficient retrieval in performing 3D stencil calculations. An apparatus to perform a stencil calculation includes a processor component, a storage communicatively coupled to the processor component, and an interleaving component for execution by the processor component to interleave storage of data of cells of adjacent rows of a first plane with data of cells of adjacent rows of an adjacent second plane of a 3D array among contiguous storage locations of the storage. Other embodiments are described and claimed.