Tiled Compute Kernels for Graphics Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current graphics processing systems face inefficiencies in processing graphics data due to limitations in tile-based architectures, which can lead to increased memory bandwidth usage and reduced performance in executing compute tasks alongside render passes.
Innovation Solution
Implementing a tiled compute kernel approach that identifies and tiles compute kernels based on localized thread groups and data access patterns, allowing for simultaneous execution with render passes and reducing memory bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional fixed function computational units are used for graphics processing, then specific graphics operations can be performed reliably, but the system lacks versatility to support a wider variety of operations
Solution Approach 1:
The patent implements a unified computational architecture where the same programmable compute units handle both traditional graphics operations (vertex shading, fragment shading) and general-purpose compute tasks. This multi-functional design eliminates the need for separate fixed-function hardware blocks, allowing a single processor to perform diverse operations while maintaining manageable complexity through standardized instruction handling
2Productivity
If tile-based processing is implemented, then memory bandwidth usage increases for certain operations, but the architecture enables efficient localized processing
Solution Approach 1:
The patent divides the screen space into discrete tiles and processes each tile independently through dedicated thread groups. This segmentation allows compute operations to be confined to specific tile regions, enabling the system to access only the memory portions corresponding to active tiles rather than flushing entire frame buffers, thereby reducing overall memory bandwidth consumption while maintaining localized processing efficiency
Solution Approach 2:
The implementation applies different processing strategies to different spatial regions through tile-based organization. Each tile can be processed with optimized memory access patterns tailored to its specific computational needs, allowing efficient use of memory bandwidth by accessing only locally relevant data rather than global memory spaces
3Productivity
If compute kernels are executed separately from render passes, then compute tasks can be performed, but performance decreases due to increased memory bandwidth usage
Solution Approach 1:
The patent merges compute kernel execution with render pass execution by organizing both operations to operate on the same tile structure. Compute thread groups and render thread groups are coordinated to process corresponding tiles simultaneously or in tight sequence, allowing intermediate compute results to be retained in local tile buffers rather than written to global memory. This combining eliminates unnecessary memory bandwidth consumption while maintaining both compute and rendering productivity
Data Source
AI summary
An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.