Tiled Datamesh Architecture for Semiconductor Latency Reduction
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Solution Overview
Problem
Current circuit routing tools face inefficiencies in routing and analyzing paths for large semiconductor dies with many subchips, leading to high latency and significant design rework, as they cannot accurately identify non-default routes for critical signals, requiring manual intervention and extensive computing resources.
Innovation Solution
A custom interconnect layout tool utilizing non-default routes (NDR) with specific routing rules for critical signals, generating a connectivity matrix for timing analysis, and iteratively updating constraints to meet latency requirements, allowing for efficient routing and analysis at the subchip level before integrating into a single die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional circuit routing tools are used to route and analyze paths in large aggregate circuit designs, then routing coverage is achieved, but routing and analysis time becomes excessively long (many hours per die with multiple iterations)
Solution Approach 1:
The patent segments the large aggregate circuit design into smaller sub-chip units, each with its own routing and timing analysis. This allows parallel processing of multiple sub-chips and enables timing analysis to be performed at the sub-chip level before final integration, dramatically reducing total analysis time compared to analyzing the entire die as a single unit.
Solution Approach 2:
The patent performs routing and timing analysis on individual sub-chips before final die-level integration. This preliminary action identifies and resolves routing issues early in the design process, avoiding the need for time-consuming re-analysis of the entire die layout and enabling earlier detection of timing violations.
2Reliability
If timing analysis is performed at the top level of the semiconductor die, then complete die-level timing verification is achieved, but the analysis must wait until later in the development process when all processors are analyzed at one time, requiring significant computing resources
Solution Approach 1:
The patent divides timing analysis into sub-chip level segments that can be performed independently and in parallel. Each sub-chip undergoes timing analysis separately, allowing earlier detection of timing issues without requiring all processors to be fully integrated and analyzed simultaneously, thus reducing computational burden and enabling earlier design iteration.
Solution Approach 2:
The patent implements a feedback mechanism where timing analysis results from sub-chip level analysis are used to identify violations, which then feed back into the routing process for correction. This iterative feedback loop at the sub-chip level allows timing issues to be resolved before final die-level integration, improving overall timing reliability while reducing total analysis time.
3Speed
If non-default routes (NDR) are used to reduce latency for critical signals, then routing speed is improved, but NDR are a limited resource and must be used only when absolutely required
Solution Approach 1:
The patent applies different routing strategies to different signals based on their criticality. Non-default routes (NDR) are reserved specifically for identified critical signals that require low latency, while non-critical signals use standard routing resources. This local differentiation optimizes speed for critical paths without unnecessarily consuming limited NDR resources for all signals.
Solution Approach 2:
The patent dynamically adjusts routing parameters based on signal characteristics and timing requirements. By analyzing signal criticality and timing constraints, the system changes routing parameters to allocate NDR resources only where necessary, optimizing the balance between routing speed and resource utilization rather than applying a uniform routing strategy to all signals.
4Manufacturing precision
If manual custom routing is performed on critical signals to optimize performance, then routing precision is improved, but the process requires significant manual intervention and increases design complexity
Solution Approach 1:
The patent implements an automated system that identifies critical signals, selects appropriate routing strategies, and performs routing optimization without requiring manual intervention. The system automatically analyzes timing requirements, identifies signals needing NDR, and configures routing paths, thereby achieving high routing precision while eliminating the complexity and time consumption of manual custom routing processes.
Data Source
AI summary
Methods and systems herein can efficiently interconnect processors through a custom grid (a data mesh) utilizing upper metal layer routing in a semiconductor die design to minimize latency. A computer-implemented method of routing interconnects on a semiconductor die includes receiving a set of non-default routes and associated routing rules; identifying a set of critical signals for feedthrough on the set of non-default routes; generating a connectivity matrix including a set of resulting routes, the resulting routes routing the set of critical signals through the set of non-default routes; generating a timing analysis of the connectivity matrix based on a set of latency requirements; responsive to determining that the timing analysis is not compliant with the latency requirements, generating a set of routing constraints; and updating the associated routing rules to include the set of routing constraints.