Tiled Electronic Units Buffer Layer Thermal Expansion Management

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Solution Overview

Problem

Tiled electronic systems face damage due to thermal expansion when adjacent units are too close, leading to potential cracking from environmental heat or operational heat generated during system use.

Innovation Solution

The solution involves maintaining a minimum distance between adjacent electronic units, calculated using specific equations (d≥8.75×10-5×W1×W2/(W1+W2), where d is the distance and W1 and W2 are the widths of the units in different directions, to prevent damage from thermal expansion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If two adjacent electronic units are arranged close to each other, then the appearance is more attractive, but the system may be damaged due to thermal expansion

Engineering Contradiction:
ImproveappearanceVSAvoiddamage resistance
Core Design Contradiction:
ShapeVSReliability

Solution Approach 1:

A buffer layer is introduced between adjacent electronic units to act as an intermediary that absorbs thermal expansion forces. The buffer layer comprises a first buffer layer and a second buffer layer with different Young's moduli, creating a gradient structure that effectively manages thermal stress while maintaining close spacing for aesthetic purposes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The Young's modulus of the buffer layer is gradually changed from the first buffer layer to the second buffer layer, creating a gradient in mechanical properties. This parameter change allows the buffer structure to adapt to thermal expansion forces while supporting the electronic units, resolving the contradiction between close spacing and damage resistance.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a buffer layer with uniform Young's modulus is used, then the structure is simple, but it cannot effectively handle thermal expansion forces

Engineering Contradiction:
Improvebuffer layer structureVSAvoidthermal expansion resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

Different regions of the buffer layer are assigned different Young's moduli to match the local requirements of adjacent electronic units. The first buffer layer has a higher Young's modulus to match rigid substrates, while the second buffer layer has a lower Young's modulus to match flexible substrates, creating a localized quality distribution that optimizes thermal stress management.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The Young's modulus parameter is changed across the buffer layer structure, creating a gradient from the first buffer layer to the second buffer layer. This parameter change enables the buffer structure to effectively handle thermal expansion forces by providing appropriate mechanical compliance at different locations.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates the risk of damage by ensuring adequate spacing between units, thereby preventing cracking and ensuring the stability of the tiled electronic system across various substrate materials and operational conditions.

Implementation Method 1

the damage problem caused by thermal expansion can be improved

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

a first buffer layer and a second buffer layer, the Young's modulus of the first buffer layer is larger than the Young's modulus of the second buffer layer

Methodology Applied
Scientific EffectElasticity: Elasticity

Data Source

PatentUS10854706B2Tiled electronic system and tiled electronic unit
Publication Date: 2020.12.01 INNOLUX CORP
  • US10854706B2 patent drawing
  • US10854706B2 patent drawing
  • US10854706B2 patent drawing

AI summary

A tiled electronic system is disclosed, which includes: a plurality of electronic units including a first electronic unit and a second electronic unit, wherein the second electronic unit is separated from the first electronic unit by a distance in a first direction, wherein the distance is conformed to the following equation (I):d≥8.75×10-5×W⁢⁢1×W⁢⁢12(W⁢⁢12+W⁢⁢22)(I)wherein d is the distance, W1 is a width of the first electronic unit in the first direction, and W2 is a width of the first electronic unit in a second direction perpendicular to the first direction.