Tiled FEC Concatenation for Low Error Floors and Stable Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
LDPC codes exhibit small but non-negligible decoding errors and high uncertainty in decoding time, especially at low bit error rates, which is undesirable for high-performance communication systems.
Innovation Solution
A tiled concatenation system is employed, comprising an outer encoder, framer, and inner LDPC encoder, which balances high and low quality bits among tiles, and uses an interleaver to rearrange bits, reducing error floors and variance in decoding iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are used for error correction, then decoding errors are reduced, but decoding time becomes highly uncertain and error floors remain at unacceptable levels
Solution Approach 1:
The patent segments the encoded bit stream into multiple tiles and applies different interleaving strategies to different tile types (high-quality vs. low-quality bits). This segmentation allows the system to handle different error patterns separately, reducing overall decoding uncertainty and eliminating error floors by ensuring all tiles have comparable decoding characteristics.
Solution Approach 2:
The patent introduces a two-dimensional tile structure with rows and columns, transforming the one-dimensional bit stream into a multi-dimensional arrangement. This dimensional change enables sophisticated interleaving patterns that distribute errors more effectively across the code block, resolving the contradiction between reliability and decoding time predictability.
2Reliability
If conventional error correction coding is used, then implementation is simple, but error floors prevent achievement of ultra-low bit error rates required for optical communication
Solution Approach 1:
The patent divides the code block into multiple tiles with different quality characteristics, allowing targeted error correction strategies for each segment. This segmentation enables the system to achieve ultra-low BER by addressing error patterns in different regions separately, while maintaining manageable complexity through modular processing.
Solution Approach 2:
The patent changes the interleaving parameter (interleaver depth) based on tile quality, applying different interleaving strengths to high-quality and low-quality tiles. This parameter adaptation allows the system to optimize error correction for each tile type, achieving the required ultra-low BER without uniformly increasing complexity across the entire system.
3Reliability
If high interleaving depth is used to reduce error floors, then bit error rate improves, but decoding complexity and time increase significantly
Solution Approach 1:
The patent applies different interleaving depths to different tiles based on their local quality characteristics. High-quality tiles receive lighter interleaving while low-quality tiles receive stronger interleaving, optimizing the overall error correction performance without uniformly increasing complexity. This local adaptation resolves the contradiction between achieving low BER and maintaining manageable decoding complexity.
Solution Approach 2:
The patent dynamically adjusts the interleaving parameter (interleaver depth) based on the quality metric of each tile. By changing this parameter locally rather than applying a fixed high interleaving depth to all tiles, the system achieves the required bit error rate performance while avoiding the proportional increase in decoding complexity that would result from uniform high-strength interleaving.
Data Source
AI summary
In part, in one aspect, the disclosure relates to a tiled concatenation system. The system may include an encoder system comprising one or more outer encoders, wherein at least one outer encoder is configured to generate n bits from k bits; a framer comprising an input, wherein the input receives T groups of n bits, wherein the framer is configured to rearrange the T groups of n bits to generate a set of T tiles, wherein each tile comprises L*C bits to generate a frame comprising L rows of K bits, the framer configured to rearrange a fraction of C bits per tile per row of each frame such that the fraction of high quality and low quality bits at the encoder output will be balanced among the tiles using an inner encoder; and the inner encoder comprising the fraction of C bits.