Tiled IC Voltage Calibration Using Test-Time Waveform Coefficients
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Solution Overview
Problem
In integrated circuits with numerous tiles, such as GPUs, the calibration of analog comparators to correct voltage offsets is cumbersome and time-consuming, significantly impacting startup performance due to the susceptibility of CMOS comparators to voltage offsets.
Innovation Solution
A hardware controller is used, divided into a test time controller and a boot time controller, to efficiently determine and adjust voltage offsets across multiple tiles, allowing for rapid calibration and minimizing the need for extensive firmware intervention during startup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog comparators are used in each tile for voltage regulation, then local voltage control accuracy is improved, but voltage offsets in CMOS comparators require time-consuming calibration that impacts startup performance
Solution Approach 1:
The patent performs comparator offset calibration during manufacturing test time rather than during system startup. Test time calibration circuits and procedures are executed before the product is shipped, so that when the system boots up, the comparators are already calibrated and no time-consuming calibration is needed during startup.
Solution Approach 2:
The patent replaces the traditional software-based calibration approach (which would run during startup) with hardware-based test time calibration circuits. This includes dedicated calibration circuitry that can be activated during manufacturing testing to perform offset measurements and store calibration data in non-volatile memory.
2Measurement precision
If offset calibration is performed when the integrated circuit starts, then comparator accuracy is corrected, but the calibration process is cumbersome and very time consuming
Solution Approach 1:
The calibration process is moved from runtime (startup) to pre-runtime (manufacturing test) phase. During test time, comprehensive calibration can be performed without time constraints, and the results are stored for use during actual operation, eliminating the need for fast runtime calibration.
Solution Approach 2:
The system uses dedicated calibration circuitry and automated test procedures that perform calibration without requiring extensive firmware intervention or manual processes. The calibration is self-contained within the hardware, using internal resources to measure and correct offsets.
3Measurement precision
If extensive firmware intervention is used for calibration, then offset correction can be performed, but startup time is significantly increased
Solution Approach 1:
The patent replaces software/firmware-based calibration with hardware-based calibration circuits. The test time controller and calibration circuits are implemented in hardware, allowing calibration to be performed rapidly during manufacturing testing without requiring firmware execution during startup.
Solution Approach 2:
All necessary calibration operations are completed during manufacturing test time before the product reaches the customer. Calibration data is stored in non-volatile memory or encoded into the hardware, so that when the system starts up, no firmware intervention is needed for calibration.
Data Source
AI summary
An integrated circuit includes a plurality of tiles receiving a power supply voltage, each having a corresponding analog circuit and operates in response to a first voltage, and a hardware controller receiving a voltage identification code and provides the first voltage to each of the plurality of tiles in response thereto. The hardware controller comprises a test time controller determining coefficients of a waveform that describes an average correspondence between the power supply voltage and the first voltage for the plurality of tiles, and a boot time controller determining a respective error signal indicating an error between the waveform and a respective actual waveform for each of the plurality of tiles, and providing the respective error signal to the corresponding analog circuit of each of the plurality of tiles. The corresponding analog circuit of each of the plurality of tiles adjusts the first voltage according to the respective error signal.