Tiled IC Memory Addressing via Switch Routing
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Solution Overview
Problem
The increasing costs and performance limitations of ASICs have led to the use of FPGAs, which are more expensive and power-hungry, while lacking the performance of ASICs, and there is a need for a solution that combines the reconfigurability of FPGAs with the performance and capability of ASICs in a parallel processing environment.
Innovation Solution
A tiled integrated circuit architecture comprising multiple tiles, each with a processor and a switch for data forwarding, along with memory interface modules that access external memory using physical memory addresses and unique identifiers, enabling efficient memory access and routing across the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used to achieve reconfigurability, then adaptability is improved, but performance deteriorates and power consumption increases
Solution Approach 1:
The integrated circuit is divided into multiple tiles, each containing processors and memory interface modules. This segmentation allows different tiles to specialize in specific functions, with some tiles handling memory access while others perform computation, thereby achieving both reconfigurability and high performance through functional division.
Solution Approach 2:
Switches are introduced as intermediary components between processors and memory interface modules. These switches manage data routing and coordination between different tiles, enabling efficient communication and data transfer while maintaining the reconfigurable architecture's flexibility.
2Adaptability or versatility
If FPGAs are used to achieve reconfigurability, then adaptability is improved, but power consumption increases
Solution Approach 1:
By segmenting the system into multiple tiles with dedicated memory interface modules, the patent enables more efficient power management. Not all tiles need to be fully active simultaneously, allowing the system to power down or idle specific tiles when not needed, thereby reducing overall power consumption while maintaining reconfigurability.
3Productivity
If multiple memory interface modules are added to access external memory, then memory access capability is improved, but device complexity increases
Solution Approach 1:
The memory access function is segmented and distributed across multiple memory interface modules located in different tiles. Each module handles access to specific external memory, and the switches coordinate which module should respond to which memory access request. This distribution increases total memory access capability while managing complexity through modular organization.
Solution Approach 2:
Switches serve as intermediaries that manage communication between processors and multiple memory interface modules. The switches handle address translation, data routing, and coordination between multiple memory interfaces, thereby increasing memory access capability while the switches absorb the complexity management.
Data Source
AI summary
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further includes a plurality of memory interface modules including circuitry to access a respective external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to access an address in an external memory by sending from the switch a packet that includes a physical memory address that includes the external memory address and information identifying the corresponding external memory.