Tiled Processor Mesh Routing Around Faulty IC Tiles
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Solution Overview
Problem
The high cost and power consumption of Field Programmable Gate Arrays (FPGAs) compared to Application Specific Integrated Circuits (ASICs), along with their lower performance and reconfigurability challenges, necessitate a more efficient method for managing yield in parallel processing integrated circuits.
Innovation Solution
A tiled integrated circuit architecture that includes a network of processor tiles with switches, allowing for the formation of data paths to preserve communication even when faulty tiles are identified, by blowing fuses or setting control information in non-volatile memory, thereby maintaining mesh network topology and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used to provide reconfigurability, then adaptability is improved, but cost and power consumption increase
Solution Approach 1:
The integrated circuit is divided into multiple independent tiles, each with its own processor and switch. This segmentation allows individual tiles to be configured independently, providing reconfigurability at the tile level while reducing overall power consumption compared to fully reconfigurable FPGAs. The segmentation also enables fault isolation and selective operation of functional tiles.
Solution Approach 2:
Each tile in the array has identical basic structure (processor and switch), but individual tiles can be selectively enabled or disabled based on functional requirements and fault status. This local quality approach allows the system to provide reconfigurability only where needed, reducing unnecessary power consumption in non-functional tiles.
2Reliability
If faulty tiles are discarded during manufacturing, then reliability is improved, but yield decreases
Solution Approach 1:
When a tile is found to be faulty during manufacturing testing, instead of discarding the entire integrated circuit, the system recovers by configuring the faulty tile to pass signals through to adjacent tiles. This allows the circuit to be salvaged and maintained in production, significantly improving manufacturing yield while preserving overall circuit functionality.
Solution Approach 2:
The system dynamically reconfigures data paths based on detected faults. During manufacturing testing, when a faulty tile is identified, the configuration is dynamically changed to route signals around the faulty tile through neighboring tiles, allowing the circuit to adapt to manufacturing variations and improve yield.
3Productivity
If data paths are rerouted around faulty tiles, then yield is improved, but network topology complexity increases
Solution Approach 1:
Each switch in the tile array is designed with universal functionality to handle both normal data routing and fault bypass operations. The switches can operate in multiple modes: standard mesh network routing, fault bypass mode, and test mode. This multi-functionality reduces the need for specialized bypass circuitry and minimizes overall system complexity while improving yield.
4Reliability
If mesh network topology is preserved despite faulty tiles, then communication reliability is improved, but path length increases
Solution Approach 1:
When a tile in the mesh network is faulty, the system can route data around the fault by transitioning to a different dimensional path. Instead of routing only through adjacent tiles in the original mesh pattern, data can be routed through tiles in perpendicular directions or through multiple hops that maintain the mesh topology while achieving communication continuity despite the fault.
Data Source
AI summary
A method for manufacturing an integrated circuit is described. The integrated circuit comprises a plurality of tiles, each tile comprising a processor and a switch coupled to neighboring tiles to form a network of tiles. The method includes identifying at least one tile that includes a fault, and forming data paths through one or more tiles to preserve communication in the network.