Tiled Neural Processor With In-Memory Crossbar Computing
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Solution Overview
Problem
Traditional computer architectures are not optimal for implementing neural networks due to the von Neumann bottleneck and lack of general-purpose designs, limiting their efficiency in emerging applications like image classification and malware analysis.
Innovation Solution
A computer processor with a tiled array architecture and a compact, power-efficient comparator design, utilizing memristor technology for dynamic weight programming and on-chip learning, allowing for flexible and efficient implementation of neural networks across various array sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional von Neumann architecture is used, then general-purpose computing is achieved, but efficiency for neural network operations deteriorates due to the von Neumann bottleneck
Solution Approach 1:
The processor is divided into multiple independent tiles, each capable of performing neural network operations. This segmentation allows parallel processing of different neural network layers or batches, significantly improving throughput while maintaining the ability to handle various computational tasks through flexible tile configuration.
Solution Approach 2:
Each tile is designed as a universal computing unit that can perform multiple functions including MACC operations, weight updates, and activation functions. The same hardware structure handles different neural network operations, eliminating the need for specialized circuits for each function while maintaining high efficiency.
2Productivity
If specialized neural network hardware is implemented, then processing efficiency improves, but adaptability to different applications deteriorates
Solution Approach 1:
The processor employs dynamic configuration capabilities where tiles can be programmatically assigned to different neural network layers, activation functions, and operational modes. This dynamic reconfigurability allows the same hardware to efficiently process different types of neural networks (CNN, RNN, Transformer) and various applications (image classification, NLP, speech recognition) without physical reconfiguration.
3Productivity
If more computational resources are allocated, then processing performance improves, but power consumption increases
Solution Approach 1:
The processor extracts and implements MACC operations directly within the memory array using resistive crossbars, eliminating the need to move data between separate memory and processing units. This in-memory computing approach dramatically reduces energy consumption associated with data transfer while maintaining high computational performance.
Solution Approach 2:
Memory and processing functions are merged into a single integrated tile structure where resistive crossbars perform both storage and computation. This merging eliminates the von Neumann bottleneck and reduces overall power consumption by consolidating operations that previously required separate memory access and processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and flexible implementation of neural networks, overcoming the limitations of traditional architectures by providing a general-purpose neural processor capable of handling diverse applications with reduced power consumption and increased performance.
Implementation Method 1
The neuron includes a first bit line, a second bit line, a programmable resistor connecting the voltage signal to the first bit line
Implementation Method 2
a comparator configured to receive inputs from the two bit lines and to output a voltage, in the event a bypass condition is not active
Implementation Method 3
a programming circuit configured to set a resistance value of the programmable resistor
Data Source
AI summary
A computer processor includes an on-chip network and a plurality of tiles. Each tile includes an input circuit to receive a voltage signal from the network, and a crossbar array, including at least one neuron. The neuron includes first and second bit lines, a programmable resistor connecting the voltage signal to the first bit line, and a comparator to receive inputs from the two bit lines and to output a voltage, when a bypass condition is not active. Each tile includes a programming circuit to set a resistance value of the resistor, a pass-through circuit to provide the voltage signal to an input circuit of a first additional tile, when a pass-through condition is active, a bypass circuit to provide values of the bit lines to a second additional tile, when the bypass condition is active; and at least one output circuit to provide an output signal to the network.