Tiled Processor Cache Coherence via Interconnect
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Solution Overview
Problem
In parallel processing environments, managing cache memory efficiently is challenging due to high costs and performance issues associated with Field Programmable Gate Arrays (FPGAs) compared to Application Specific Integrated Circuits (ASICs), and existing solutions fail to effectively utilize off-chip bandwidth and reduce cache coherence overhead.
Innovation Solution
A tiled integrated circuit architecture with multiple processor cores and an interconnection network that allows processor cores to access each other's caches directly, reducing the need for large local caches and maintaining cache coherence, thereby optimizing on-chip data access and bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If each processor core maintains a large local cache to ensure fast data access, then data access speed is improved, but on-chip area and cost increase
Solution Approach 1:
The patent merges the cache resources of multiple processor cores into a shared cache system accessible through the interconnection network. Instead of each core having a large private cache, cores can access cached data from other cores' caches via message passing, effectively combining the total cache resource pool while maintaining fast access through direct network paths.
Solution Approach 2:
The interconnection network is designed to serve multiple functions: it enables both data transmission between processors and cache access operations. The same network infrastructure supports general-purpose communication and specific cache memory access, eliminating the need for separate cache coherence networks or dedicated cache access paths.
2Adaptability or versatility
If FPGAs are used to achieve reconfigurability, then adaptability is improved, but performance and power consumption worsen
Solution Approach 1:
The system segments the reconfiguration capability into discrete processor cores that can be individually configured or replaced. Each core can be programmed independently, allowing flexible system configuration without requiring entire FPGA-like reconfigurability, thus achieving adaptability with ASIC-level performance.
Solution Approach 2:
The interconnection network acts as an intermediary that enables flexible data routing and communication patterns between processor cores. This allows the system to adapt to different computational workloads and data access patterns through software-controlled network routing rather than hardware reconfiguration, maintaining high performance while achieving adaptability.
3Speed
If direct cache access between processor cores is implemented, then on-chip data access efficiency is improved, but cache coherence overhead increases
Solution Approach 1:
The system implements self-service cache coherence management where processor cores autonomously handle cache access requests and coherence maintenance. Each core independently manages its own cache state and participates in coherence protocols through standard message passing, eliminating the need for complex centralized coherence controllers while maintaining efficient access.
Solution Approach 2:
The message passing interface provides feedback mechanisms that allow processor cores to track the state of cached data across the system. Through acknowledgment messages and status reporting in the interconnection network, cores can determine when cache lines are valid, modified, or need to be invalidated, enabling efficient coherence management without centralized control.
Data Source
AI summary
An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.