Tiled Processor Architecture With DMA Control for Parallel Memory Access
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Solution Overview
Problem
The high cost and performance limitations of Field Programmable Gate Arrays (FPGAs) compared to Application Specific Integrated Circuits (ASICs) in implementing customized logic circuits, along with the need for efficient reconfigurability and power management in parallel processing environments.
Innovation Solution
A tiled integrated circuit architecture comprising multiple tiles, each with a pipelined processor and a switch for data forwarding, enabling efficient data communication and parallel processing, along with a method for compiling programs to optimize execution across tiles, including partitioning and scheduling instructions for parallel execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used to implement customized logic circuits, then reconfigurability is improved, but cost and power consumption increase while performance deteriorates
Solution Approach 1:
The system is divided into multiple independent tiles, each containing a processor and switch. This segmentation allows parallel execution across tiles while maintaining reconfigurability at the tile level, resolving the contradiction between system-level adaptability and performance by enabling fine-grained parallelism.
Solution Approach 2:
The switch within each tile dynamically routes data packets between processors and memory based on real-time requirements. This dynamic routing capability provides reconfigurability without the performance penalty of FPGAs, as the dynamic switching occurs at hardware speed rather than requiring full logic reconfiguration.
2Adaptability or versatility
If FPGAs are used to implement customized logic circuits, then reconfigurability is improved, but manufacturing cost increases
Solution Approach 1:
By segmenting the system into standardized tiles that can be manufactured using conventional ASIC processes, the design achieves reconfigurability through software-controlled switching rather than expensive FPGA fabrication. This segmentation enables cost-effective manufacturing while maintaining adaptability.
Solution Approach 2:
Each tile contains a universal processor and switch that can be configured for different applications through software. This multi-functionality eliminates the need for custom ASIC fabrication for each application, reducing manufacturing costs while maintaining reconfigurability.
3Adaptability or versatility
If FPGAs are used to implement customized logic circuits, then reconfigurability is improved, but power consumption increases
Solution Approach 1:
The switch dynamically routes data only when needed, allowing idle tiles to enter low-power states. This dynamic operation reduces overall power consumption compared to FPGAs, which consume power continuously to maintain reconfigurable logic structures even when not actively changing configuration.
Solution Approach 2:
Reconfigurability is implemented locally within each tile through the switch, rather than requiring global reconfiguration of the entire system. This localized approach reduces power consumption by limiting the active reconfiguration logic to only the necessary components.
4Productivity
If data is forwarded based on multiple instruction streams, then processing efficiency is improved, but control complexity increases
Solution Approach 1:
The switch acts as an intermediary that manages multiple instruction streams independently. It receives routing instructions from processors and memory, then efficiently routes data packets without requiring complex coordination between instruction streams. This intermediary approach simplifies control complexity while maintaining high processing efficiency.
Solution Approach 2:
The control of multiple instruction streams is segmented and distributed to individual switches in each tile rather than centralized. Each switch independently manages its own routing based on local instructions, reducing overall control complexity while enabling parallel processing efficiency.
Data Source
AI summary
An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch. Also disclosed is a direct memory access (DMA) scheme in which sizes of DMA transfers are limited according to whether a cache miss has occurred.