Tiled Processor Interconnection Network Routing
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Solution Overview
Problem
The increasing costs and performance limitations of ASICs have led to the use of FPGAs, which are more expensive and power-hungry, while lacking the performance and reconfigurability of ASICs.
Innovation Solution
A tiled integrated circuit architecture with a plurality of processor cores and an interconnection network that routes data based on destination information, utilizing a two-dimensional mesh network for efficient data forwarding and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used to achieve reconfigurability, then adaptability is improved, but power consumption and cost increase
Solution Approach 1:
The system is divided into multiple processor cores organized in a tiled architecture, where each core can be independently configured. This segmentation allows partial reconfiguration of only the necessary cores rather than the entire system, reducing power consumption while maintaining adaptability.
Solution Approach 2:
The tiled processor architecture enables dynamic reconfiguration of processor cores at runtime. Cores can be enabled or disabled based on computational needs, allowing the system to adapt to different workloads while optimizing power consumption by activating only the required cores.
2Adaptability or versatility
If FPGAs are used to achieve reconfigurability, then adaptability is improved, but performance deteriorates
Solution Approach 1:
The tiled architecture segments the processor into multiple independent cores that can be configured for specific tasks. This allows high-performance ASIC-like behavior for dedicated functions while maintaining FPGA-like reconfigurability for other cores, thus improving overall performance without sacrificing adaptability.
Solution Approach 2:
Different processor cores can have different levels of configuration and performance optimization. Critical performance paths can be implemented with fixed, high-performance logic, while less critical functions retain reconfigurability, achieving local quality optimization that balances performance and adaptability.
3Adaptability or versatility
If FPGAs are used to achieve reconfigurability, then adaptability is improved, but cost increases
Solution Approach 1:
The tiled processor architecture allows the system to be manufactured as a standard integrated circuit with multiple identical or heterogeneous cores. This segmentation enables volume manufacturing benefits similar to ASICs while retaining reconfigurability capabilities, thereby reducing cost compared to traditional FPGAs.
Solution Approach 2:
The tiled processor cores are designed to be universal and can be configured for multiple different functions. This multi-functionality reduces the need for multiple specialized chips, allowing a single reconfigurable processor family to replace multiple ASICs and FPGAs, thus lowering overall system cost.
4Adaptability or versatility
If data is routed through multiple processor cores, then routing flexibility is improved, but data transmission time increases
Solution Approach 1:
The interconnection network is configured with pre-established routing paths and switching fabric that can quickly redirect data. Routing decisions are made in advance at the tile level, and the network infrastructure is prepared to handle multiple routing scenarios, reducing actual data transmission time while maintaining flexibility.
Solution Approach 2:
The interconnection network acts as an intermediary between processor cores, providing efficient data transmission paths. The network includes switching elements and buffers that can quickly forward data between tiles, reducing the time penalty associated with multi-core routing while maintaining routing flexibility.
Data Source
AI summary
An apparatus comprises a plurality of processor cores, and an interconnection network to route data among the processor cores based on destination information in the data. The processor cores are configured to forward the data to a final destination if the destination information indicates that a destination processor core has been reached, or to forward the data to other processor cores if the destination information indicates that a destination processor core has not been reached. The final destination is one of a plurality of destinations indicated by the destination information, the destinations including a plurality of portions of the destination processor core.