Tiled Parallel Processor Power Gating with Timer Wake-Up
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Solution Overview
Problem
FPGAs are power-hungry and performance-wise inferior to ASICs, despite being reconfigurable, which makes them costly and inefficient for parallel processing environments.
Innovation Solution
A tiled integrated circuit architecture with low power modes that allow processors or switches to be powered down, using a timer to efficiently manage power consumption and reduce energy usage while maintaining reconfigurability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used for reconfigurability, then adaptability is improved, but power consumption increases and performance deteriorates
Solution Approach 1:
The system is divided into multiple independent tiles, each capable of autonomous power management. Individual tiles can be powered down when not needed, while others remain active. This segmentation allows the system to maintain reconfigurability through active tiles while reducing overall power consumption by deactivating inactive portions of the circuit.
Solution Approach 2:
The power state of each tile is dynamically adjusted based on its activity status. Tiles transition between active and low-power states as needed, allowing the system to adapt its power consumption to actual workload requirements while maintaining the capability for reconfiguration when tiles are activated.
2Adaptability or versatility
If FPGAs are used for reconfigurability, then adaptability is improved, but performance deteriorates
Solution Approach 1:
Different tiles can operate in different states simultaneously - some tiles remain active and maintain full performance capability, while others are powered down. This local differentiation allows the system to achieve reconfigurability through active tiles without sacrificing overall performance, as only the necessary portion of the system needs to be active at any given time.
Solution Approach 2:
By segmenting the system into independent tiles with dedicated processing resources, the system can activate only the tiles needed for current computations. This prevents performance degradation by ensuring that active tiles operate at full capacity while inactive tiles consume minimal resources.
3Loss of energy
If tiles are powered down to reduce power consumption, then energy efficiency is improved, but processing capability deteriorates
Solution Approach 1:
The system dynamically manages power states based on actual processing needs. Tiles transition to low-power modes when idle and activate when needed, ensuring that processing capability is maintained for active tiles while achieving energy efficiency through selective power down of inactive tiles.
Solution Approach 2:
Each tile is designed as a universal processing unit that can handle various computational tasks. This multi-functionality allows the system to achieve high energy efficiency by activating only the minimum number of tiles needed for current workloads, while still maintaining full processing capability through the versatile design of individual tiles.
4Loss of energy
If switches are powered down to reduce power consumption, then energy efficiency is improved, but data forwarding capability deteriorates
Solution Approach 1:
The switching infrastructure is segmented into tile-local switches that can be independently controlled. When a tile is inactive, its local switch is powered down to save energy. When the tile becomes active, the switch activates to restore data forwarding capability, ensuring that switching functionality is maintained for active tiles while achieving energy efficiency.
Solution Approach 2:
The tile-local switch acts as an intermediary between the processor and the inter-tile network. By controlling the power state of this intermediary component based on tile activity, the system maintains data forwarding capability when needed while achieving energy efficiency by placing switches in low-power modes during idle periods.
Data Source
AI summary
An integrated circuit includes a plurality of tiles. Each tile includes a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; and a timer. At least some tiles include a low power mode of operation in which either the processor or the switch is able to be powered down, and the tile is able to leave the low power mode based at least in part on a value of the timer.