Tiled Sparse Matrix Layout for Cache-Efficient Multiplication

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Solution Overview

Problem

Existing technologies face challenges in efficiently processing sparse matrices due to significant overhead in storing and processing zero-value elements, which is exacerbated by increasing complexity and size of data sets in machine learning applications.

Innovation Solution

A tiling approach is employed to divide sparse matrices into submatrices, ignoring zero-value entities and processing only non-zero entries, utilizing an indexing approach for correct multiplication with dense matrices, and optimizing cache misses through rectangular tiles with optimal aspect ratios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If sparse matrices are stored using traditional formats (CSR/CSC), then complete matrix data is preserved, but memory overhead increases significantly and memory locality deteriorates

Engineering Contradiction:
Improvememory overheadVSAvoiddata completeness
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the sparse matrix into multiple tiles (sub-matrices), where each tile can be independently processed. This segmentation allows the system to focus only on non-zero tiles, reducing memory overhead while maintaining data completeness through systematic indexing that tracks the position of each tile within the original matrix structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts and processes only the non-zero tiles from the sparse matrix, ignoring zero-value tiles entirely. This extraction approach reduces memory overhead by eliminating storage and processing of redundant zero elements, while the indexing mechanism ensures that the extracted non-zero tiles can be correctly reassembled to maintain data completeness.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If all tiles including zero-value tiles are processed, then correct matrix multiplication is ensured, but processing speed decreases due to unnecessary computations

Engineering Contradiction:
Improveprocessing speedVSAvoidcomputation accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent extracts only the non-zero tiles for processing, eliminating unnecessary computations on zero-value tiles. This extraction is achieved through pre-computed indexing structures that identify which tiles contain non-zero elements, thereby improving processing speed without compromising computation accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary indexing and identification of non-zero tiles before the actual matrix multiplication operation. This preliminary action creates a roadmap of which tiles need processing, allowing the system to skip zero-value tiles during computation while ensuring that all necessary non-zero tiles are processed with correct positioning, thus maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

3Stability of the object's composition

If zero-value elements are stored, then complete matrix structure is maintained, but cache performance deteriorates due to poor memory locality

Engineering Contradiction:
Improvematrix structureVSAvoidcache performance
Core Design Contradiction:
Stability of the object's compositionVSSpeed

Solution Approach 1:

The patent segments the matrix into tiles, allowing the system to work with smaller, cache-friendly units. This segmentation improves memory locality by loading only relevant non-zero tiles into cache, reducing the amount of data that needs to be stored and accessed, thereby maintaining matrix structure through indexing while enhancing cache performance.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12613697B2Tiled compressed sparse matrix format
Publication Date: 2026.04.28 NVIDIA CORP
  • US12613697B2 patent drawing
  • US12613697B2 patent drawing
  • US12613697B2 patent drawing

AI summary

Approaches in accordance with various embodiments provide for the processing of sparse matrices for mathematical and programmatic operations. In particular, various embodiments utilize a tiling approach that divides a sparse matrix into submatrices, many of which will include only zero-value entities. These empty tiles can be ignored, and only the tiles with non-zero entries processed, which reduces resource and time requirements for the processing. An indexing approach can be used for each entity that is a combination of the tile identifier and an offset value, which enables the values to be multiplied correctly against, for example, values of a dense matrix. The tiles can be processed in parallel and the results accumulated to generate a matrix product. The matrix product can then be passed to the next step in a process or operation, such as to a next layer in a deep neural network.