Tiled Switch Matrix Permutation Circuit for Dynamic Data Routing
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Solution Overview
Problem
Existing data processing circuits are limited in their ability to perform a wide range of data pattern permutations, making them inadequate for dynamic systems that require multiple permutations, such as artificial intelligence processors.
Innovation Solution
A switch matrix circuit with a data permutation circuit comprising multiple adjacent switching blocks and switching stages that span across blocks, allowing data to be received in one pattern and output in various patterns based on switch control settings, without the need for additional control logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If custom circuits are used to perform limited data permutations, then device complexity is reduced, but adaptability deteriorates
Solution Approach 1:
The patent implements a universal permutation circuit that can perform multiple data permutation patterns (transpose, interleave, de-interleave, shuffle, etc.) using a single reconfigurable switch matrix structure. The circuit achieves this by allowing dynamic configuration of switching blocks and stages through control signals, enabling one circuit to replace multiple custom circuits for different permutation needs.
Solution Approach 2:
The permutation circuit employs dynamic reconfigurability where the switching blocks and stages can be dynamically programmed during operation to perform different permutation patterns. The control logic dynamically adjusts the routing paths and switching states based on the desired permutation operation, transforming a static circuit into a dynamically adaptable system.
2Adaptability or versatility
If a reconfigurable permutation circuit is implemented, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent divides the permutation circuit into multiple independent switching blocks arranged in a matrix, where each block contains smaller switching units. This segmentation allows the complex permutation task to be distributed across multiple simpler units, reducing the complexity of individual components while maintaining overall system versatility through their coordinated operation.
Solution Approach 2:
The circuit architecture employs a nested structure where switching blocks are organized in hierarchical stages, with smaller switching units nested within larger block structures. This nested organization allows complex permutations to be achieved through multiple levels of simpler switching operations, managing complexity through hierarchical decomposition.
3Productivity
If multiple switching stages spanning adjacent blocks are used, then data permutation efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges multiple switching blocks into a unified switch matrix structure where adjacent blocks work together as integrated units. The switching stages span across block boundaries, combining the functionality of individual blocks into coordinated groups that process data in parallel, improving overall permutation efficiency while managing complexity through unified control.
Solution Approach 2:
The patent introduces a two-dimensional matrix arrangement of switching blocks with stages that span across blocks in both horizontal and vertical dimensions. This dimensional expansion allows data to be permuted across multiple blocks simultaneously through coordinated switching stages, increasing throughput and efficiency by utilizing spatial distribution rather than sequential processing.
Data Source
AI summary
Embodiments of the present disclosure pertain to switch matrix circuit including a data permutation circuit. In one embodiment, the switch matrix comprises a plurality of adjacent switching blocks configured along a first axis, wherein the plurality of adjacent switching blocks each receive data and switch control settings along a second axis. The switch matrix includes a permutation circuit comprising, in each switching block, a plurality of switching stages spanning a plurality of adjacent switching blocks and at least one switching stage that does not span to adjacent switching blocks. The permutation circuit receives data in a first pattern and outputs the data in a second pattern. The data permutation performed by the switching stages is based on the particular switch control settings received in the adjacent switching blocks along the second axis.