Tiled Switch Architecture for Parallel Data Transfer and Lower Power
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Solution Overview
Problem
Existing integrated circuits face challenges in efficiently processing large instruction streams and managing power consumption in parallel processing environments, with FPGAs being more expensive and power-hungry compared to ASICs, while lacking the performance of ASICs.
Innovation Solution
A tiled integrated circuit architecture featuring a plurality of tiles, each with a processor and a switch that includes switching circuitry for forwarding data and operating independently, with a switch memory that stores instruction streams for respective output ports, allowing for efficient processing of large instruction streams and asynchronous clocking of tile sets to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used to provide reconfigurability, then adaptability is improved, but power consumption increases and performance deteriorates compared to ASICs
Solution Approach 1:
The system is divided into multiple independent tiles, each with its own processor and switch. This segmentation allows individual tiles to be powered down or operated asynchronously, reducing overall power consumption while maintaining reconfigurability through the modular architecture.
Solution Approach 2:
The switch operates in operand decoupling mode, allowing independent instruction streams for different output ports. This dynamic operation mode enables efficient processing of large instruction streams while reducing power consumption by avoiding unnecessary synchronized operations across all tiles.
2Adaptability or versatility
If FPGAs are used to provide reconfigurability, then adaptability is improved, but performance deteriorates compared to ASICs
Solution Approach 1:
By segmenting the system into independent tiles with dedicated processors and switches, each tile can operate autonomously on its own instruction stream, improving overall system throughput and performance while maintaining the reconfigurable nature of the architecture.
Solution Approach 2:
The switch memory stores pre-fetched instruction streams for multiple output ports in advance. This preliminary action allows the switch to operate efficiently without waiting for instructions to be generated in real-time, improving performance by reducing idle cycles and wait states.
3Ease of operation
If synchronous operation mode is used, then coordination among tiles is simplified, but power consumption increases
Solution Approach 1:
The system dynamically selects between synchronous and asynchronous operation modes based on workload requirements. The switch can operate in operand decoupling mode with independent instruction streams for asynchronous operation, or switch to synchronized mode when coordination is needed, optimizing power consumption while maintaining ease of operation.
Solution Approach 2:
The operational parameters of the tiles and switch can be changed dynamically. By adjusting the synchronization parameter and instruction stream fetching behavior, the system can transition between power-efficient asynchronous mode and coordination-friendly synchronous mode, resolving the contradiction between ease of operation and power consumption.
4Productivity
If large instruction streams are processed, then productivity is improved, but device complexity increases
Solution Approach 1:
The instruction stream processing is segmented into independent streams for different output ports, each managed separately by the switch memory. This segmentation allows the system to process large volumes of instructions through parallel independent streams rather than one complex monolithic stream, improving productivity while managing complexity through modular organization.
Solution Approach 2:
The switch memory pre-stores instruction streams for multiple output ports, allowing the switch to operate efficiently without real-time instruction generation. This preliminary action simplifies the processing complexity by having instructions ready in advance, while enabling the system to handle large instruction volumes through efficient memory management and pre-fetching strategies.
Data Source
AI summary
An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.