Tiled Lateral Thyristor Layout for SOI and CMOS Integration
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Solution Overview
Problem
The challenge lies in designing a thyristor that can be adapted for various applications while overcoming spatial constraints in integrated circuit layouts and the difficulty of fabricating thyristors on semiconductor-on-insulator (SOI) substrates, which limits performance and integration flexibility.
Innovation Solution
The design incorporates a thyristor tile composed of alternating PNP and NPN tiles with specific orientations and interconnect layers, allowing for flexible placement and layout within integrated circuits, and can be formed simultaneously with CMOS process flows, including on SOI wafers, enabling efficient electrical connections and scalable integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional thyristor design is used, then the device structure is simple, but spatial constraints in integrated circuit layouts severely restrict placement and layout choices, adversely affecting performance characteristics
Solution Approach 1:
The thyristor is divided into multiple discrete tiles (PNP tiles and NPN tiles) that can be independently placed and connected through interconnect layers. This segmentation allows flexible arrangement within the integrated circuit layout while maintaining the functional integrity of the thyristor device.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional structure by stacking PNP and NPN tiles in alternating layers with vertical interconnects. This dimensional change provides additional spatial freedom for placement while reducing the footprint constraint in the horizontal plane.
2Ease of manufacture
If standard fabrication processes are used, then manufacturing is straightforward, but it is generally very difficult to make a thyristor on a semiconductor-on-insulator (SOI) substrate
Solution Approach 1:
The thyristor structure is segmented into separate PNP and NPN tiles that can be independently fabricated on the SOI substrate using standard CMOS-compatible processes. This segmentation allows each tile type to be optimized for its specific fabrication requirements while maintaining compatibility with SOI technology.
Solution Approach 2:
The invention modifies fabrication parameters and process sequences to enable thyristor formation on SOI substrates. By adjusting doping profiles, oxidation conditions, and etch parameters, the process achieves successful thyristor fabrication on SOI while maintaining compatibility with existing CMOS manufacturing lines.
3Area of stationary object
If a compact thyristor design is used, then area is reduced, but interconnect complexity increases with multiple layers required for electrical connections
Solution Approach 1:
The interconnect structure utilizes the vertical dimension by stacking PNP and NPN tiles in alternating layers with vertical vias and contacts. This three-dimensional interconnection approach reduces the horizontal footprint while distributing the interconnect complexity across multiple vertical layers rather than requiring extensive horizontal routing.
Solution Approach 2:
Adjacent PNP and NPN tiles share common interconnect structures and contact regions, merging redundant elements and reducing overall interconnect complexity. The alternating tile arrangement allows shared via structures and common electrical pathways that simplify the interconnection network.
Data Source
AI summary
A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.