Tiled Video Data Memory Mapping for DRAM Refresh Optimization
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Solution Overview
Problem
Modern battery-powered handheld devices face challenges in efficiently storing and retrieving video and image data due to the overhead of accessing dynamic random access memory (DRAM), which results in reduced memory bandwidth and increased power consumption, as each DRAM row must be refreshed regardless of the data needed, leading to specific optimizations that are hardware and software dependent and difficult to integrate.
Innovation Solution
The method involves partitioning graphical data into two-dimensional tiles and mapping these tiles to a single memory row, using address transformation logic to optimize memory access, allowing concurrent access to pixels spanning multiple scan lines and reducing the need for full row refreshes, thereby improving memory access speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If graphical data is stored in standard DRAM row format, then memory capacity is maximized, but memory access speed decreases due to full row refresh requirements
Solution Approach 1:
The patent segments graphical data into two-dimensional tiles that can be mapped to single DRAM rows. This segmentation allows the system to access only the specific tile data needed rather than refreshing entire DRAM rows, thereby improving memory access speed and reducing the overhead of full row refresh operations while maintaining adequate memory capacity utilization.
2Use of energy by moving object
If standard DRAM row access is used, then memory capacity is fully utilized, but power consumption increases due to mandatory full row refresh
Solution Approach 1:
By segmenting graphical data into tiles that map to single DRAM rows, the system can perform selective refresh operations only on rows containing actively displayed tiles. This segmentation strategy significantly reduces power consumption compared to mandatory full row refresh of standard DRAM organization, while the tile mapping ensures that memory bandwidth is efficiently utilized for actual graphical data access patterns.
3Speed
If image objects are stored in hardware-specific optimized arrangements, then memory access efficiency improves, but system adaptability decreases
Solution Approach 1:
The patent implements a universal tile-based memory organization system where graphical data is divided into standardized two-dimensional tiles that can be mapped to single DRAM rows. This universal tile structure can be applied across different hardware platforms and software configurations, providing memory access efficiency benefits while maintaining system adaptability and compatibility, unlike hardware-specific optimized arrangements.
Data Source
AI summary
The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.