Tiling Configurations in Neural Network Processing Graphs

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Solution Overview

Problem

Processing large-sized images in machine learning models, such as Convolutional Neural Networks (CNNs), is computationally expensive and often requires significant memory and processing power, leading to inefficiencies and loss of information due to downsampling.

Innovation Solution

The implementation of enhanced tiling techniques within neural networks, allowing for the division of large tensors into smaller, overlapping or non-overlapping tiles, which are then processed and convolved individually, optimizing memory usage and computational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If large-sized images are processed directly in machine learning models, then processing accuracy is maintained, but memory requirements and computational burden increase significantly

Engineering Contradiction:
Improveprocessing accuracyVSAvoidmemory requirements
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent divides large input images into multiple smaller tiles or patches that can be processed independently by the neural network. Each tile is processed separately through the convolutional layers, reducing the memory footprint at any given time while maintaining the ability to reconstruct the full output by combining individual tile results.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If large-sized images are processed directly in machine learning models, then processing accuracy is maintained, but computational burden increases significantly

Engineering Contradiction:
Improveprocessing accuracyVSAvoidcomputational burden
Core Design Contradiction:
Measurement precisionVSPower

Solution Approach 1:

The patent segments large images into smaller tiles that can be processed in parallel or sequentially by the neural network. This reduces the computational burden on each processing unit while maintaining overall processing accuracy through proper handling of tile boundaries and overlapping regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies convolutional operations to each tile independently rather than processing the entire large image at once. This partial action approach allows the system to handle computationally intensive tasks in manageable portions, reducing peak computational requirements while achieving complete image processing through aggregation of tile-level results.

Inventive Principle:
Principle #16Partial or excessive action

3Quantity of substance

If downsampling is applied to reduce memory requirements, then memory usage is optimized, but information loss occurs

Engineering Contradiction:
Improvememory usageVSAvoidinformation loss
Core Design Contradiction:
Quantity of substanceVSLoss of information

Solution Approach 1:

Instead of downsampling the entire image which causes information loss, the patent segments the image into tiles that are processed at their original resolution. This maintains full information content in each tile while reducing overall memory requirements through distributed processing and selective loading of tile batches into memory.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250190749A1Multiple tiling configurations in single processing graph
Publication Date: 2025.06.12 SAMBANOVA SYSTEMS INC
  • US20250190749A1 patent drawing
  • US20250190749A1 patent drawing
  • US20250190749A1 patent drawing

AI summary

A device may pad a first input into a first padded input, read a first set of input tiles from the first padded input in a first input tiling configuration, process the first set of input tiles through a first section of a graph to generate a first set of output tiles in a first target tiling configuration, and pad the first set of output tiles to generate first set of padded output tiles. A device may arrange the first set of padded output tiles into a second input comprising a second set of input tiles, read the second set of input tiles from the second input in a second input tiling configuration, and process the second set of input tiles through a second section of the graph to generate a second set of output tiles in a second target tiling configuration, different than the first target tiling configuration.