Tiling Engine for IC Physical Design Constraint Handling

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Solution Overview

Problem

In electronic design automation, placement of circuit elements on a chip surface is challenging due to complex and non-contiguous user constraints, leading to inconsistent results across different placement engines and difficulties in diagnosing constraint-related issues.

Innovation Solution

A tiling engine transforms ambiguous user constraints into a simple placement problem by partitioning the placement area into non-overlapping geometric tiles, each with a list of cells to be placed, providing a consistent and straightforward representation for placement engines and allowing for query of user constraints that influenced each tile.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If placement engines directly process complex user constraints, then flexibility in handling diverse constraint types is improved, but consistency and reliability of placement results deteriorate

Engineering Contradiction:
Improveconstraint handling flexibilityVSAvoidplacement result consistency
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a constraint processing layer that acts as an intermediary between user constraints and placement engines. This layer standardizes complex, ambiguous user constraints into a unified constraint model that all placement engines can process consistently, thereby maintaining adaptability to diverse constraint types while ensuring reliability and consistency of placement results across different engines.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the constraint processing functionality into distinct modular components: a constraint parser that handles diverse user inputs, a constraint validator that checks for conflicts, and a constraint translator that converts constraints into a standardized format. This segmentation allows each component to specialize in specific tasks, improving overall system reliability while maintaining versatility.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If placement engines independently interpret user constraints, then ease of operation for individual engines is improved, but diagnostic capability for constraint conflicts deteriorates

Engineering Contradiction:
Improveengine independenceVSAvoidconstraint conflict diagnosis
Core Design Contradiction:
Ease of operationVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements a feedback mechanism where the constraint processing layer provides detailed information about constraint interpretation, validation results, and conflict detection back to both users and placement engines. This feedback includes specific messages about which constraints are active, how they are being applied, and where conflicts exist, thereby maintaining engine independence while dramatically improving diagnostic capability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The constraint processing layer serves as an intermediary that centralizes constraint interpretation and conflict detection logic. This allows all placement engines to operate independently with simplified constraint processing, while the intermediary layer provides unified diagnostic information about constraint conflicts, making it easy to identify and resolve issues.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If multiple placement engines use different constraint interpretations, then adaptability to various placement strategies is improved, but result reproducibility deteriorates

Engineering Contradiction:
Improveplacement strategy diversityVSAvoidplacement result reproducibility
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent changes the parameters of constraint representation from engine-specific interpretations to a standardized constraint model with well-defined parameters and semantics. This standardized model allows different placement engines to maintain their unique placement strategies and algorithms while ensuring that all engines interpret and apply user constraints in the same way, thereby achieving both adaptability to diverse strategies and reproducibility of results.

Inventive Principle:
Principle #35Parameter changes

4Measurement precision

If constraint reporting is detailed after placement, then measurement precision of constraint influence is improved, but computational cost deteriorates

Engineering Contradiction:
Improveconstraint influence analysisVSAvoidreporting computational cost
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent performs constraint analysis, validation, and conflict detection as preliminary actions during the constraint processing phase, before the actual placement computation begins. This preliminary processing identifies and reports constraint issues early, providing detailed measurement of constraint influence without requiring additional computational resources during the expensive placement phase, thereby achieving precise measurement with minimal additional computational cost.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10831964B2IC physical design using a tiling engine
Publication Date: 2020.11.10 SYNOPSYS INC
  • US10831964B2 patent drawing
  • US10831964B2 patent drawing
  • US10831964B2 patent drawing

AI summary

In general, embodiments of the present invention provide systems, methods and computer readable media for generating a tiling for a physical placement of a plurality of circuits. The method includes generating a tiling including a plurality of tiles, where each tile identifies a tile geometric area, and a list of one or more of the circuits to be placed in the tile geometric area. The tiling is based on a description of one or more user constraints, where each user constraint identifies a constraint geometric area, and a characteristic of circuits to be placed in the constraint geometric area.