Tilt Pre-amorphization Implant for Semiconductor Contact Resistance
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Solution Overview
Problem
As semiconductor devices are miniaturized, reducing contact resistance becomes increasingly challenging due to the reduced open area and increased aspect ratio of contact holes, leading to non-uniform ion implantation damage and crystalline defects, which deteriorate contact resistance characteristics and gate-induced drain leakage.
Innovation Solution
The method involves germanium tilt pre-amorphization implantation followed by boron doping and metal silicide formation, using tilt implantation angles of 1° to 45° and ion implantation energies of 0.1 keV to 60 keV, to uniformly control ion implantation damage and improve dopant activation, thereby reducing contact resistance and gate-induced drain leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ion implantation is used in miniaturized semiconductor devices, then doping can be achieved, but non-uniform ion implantation damage and crystalline defects occur, deteriorating contact resistance characteristics
Solution Approach 1:
The patent applies pre-amorphization implantation before the main doping step. A first ion implantation (e.g., silicon or germanium) is performed at a higher dose to create an amorphous layer in the semiconductor substrate. This preliminary action modifies the crystal structure to prevent channeling effects and ensure uniform distribution of subsequent dopant ions, thereby resolving the non-uniformity issue while maintaining reliable contact resistance characteristics
Solution Approach 2:
The patent replaces conventional single-step ion implantation with a multi-step process involving pre-amorphization implantation followed by secondary doping. This substitution transforms the mechanical implantation process into a controlled two-stage operation where the first stage creates a favorable structural environment for the second stage, eliminating the harmful non-uniform damage and crystalline defects
2Area of moving object
If contact hole open area is reduced to miniaturize semiconductor devices, then device scaling is achieved, but contact resistance increases due to reduced area and increased aspect ratio
Solution Approach 1:
The patent changes the physical and chemical parameters of the semiconductor substrate surface through pre-amorphization implantation. By modifying the crystal structure, doping concentration profile, and surface morphology parameters, the process enhances dopant activation and creates a more conductive contact region. This allows achieving low contact resistance even in miniaturized devices with reduced contact hole open area and increased aspect ratio
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and improves dopant activation, enhancing the performance of semiconductor devices by minimizing crystalline defects and gate-induced drain leakage.
Implementation Method 1
performing tilt implantation using a first additional dopant to form an amorphous region in the doping region
Implementation Method 2
reacting the doped amorphous region with the metal layer to form metal silicide
Data Source
AI summary
A method for fabricating a semiconductor device may include: preparing a semiconductor substrate including a doping region; performing tilt implantation using a first additional dopant to form an amorphous region in the doping region; doping a second additional dopant in the amorphous region; forming a metal layer on the doped amorphous region; and reacting the doped amorphous region with the metal layer to form metal silicide.